參數(shù)資料
型號： AM486
英文描述： Am486 Microprocessor Software User＇s Manual? 4.40MB (PDF)
中文描述： Am486微處理器軟件用戶手冊？ 4.40MB（PDF格式）
文件頁數(shù)： 23/52頁
文件大?。?/td> 1242K
代理商： AM486
Am486DE2 Microprocessor
23
For uses such as fast enabling of external I/O devices,
the SMSAVE mode permits the restarting of the I/O in-
structions and the HALT instruction. This is accom-
plished through I/O Trap Restart and Halt/Auto Halt
Restart slots. Only I/O and HALT opcodes are restart-
able. Attempts to restart any other opcode may result in
unpredictable behavior.
The System Management Interrupt hardware interface
consists of the SMI request input and the SMIACT out-
put used by the system to decode the SMRAM (see
Figure 5).
System Management Interrupt Processing
SMI is a falling-edge-triggered, non-maskable interrupt-
request signal. SMI is an asynchronous signal, but setup
and hold times must be met to guarantee recognition in
a specific clock. The SMI input does not have to remain
active until the interrupt is actually serviced. The SMI
input needs to remain active for only a single clock if the
required setup and hold times are met. SMI also works
correctly if it is held active for an arbitrary number of
clocks (see Figure 6).
The SMI input must be held inactive for at least four
clocks after it is asserted to reset the edge-triggered
logic. A subsequent SMI may not be recognized if the
SMI input is not held inactive for at least four clocks after
being asserted. SMI, like NMI, is not affected by the IF
bit in the EFLAGS register and is recognized on an in-
struction boundary. SMI does not break locked bus cy-
cles. SMI has a higher priority than NMI and is not
masked during an NMI. After SMI is recognized, the SMI
signal is masked internally until the RSM instruction is
executed and the interrupt service routine is complete.
Masking SMI prevents recursive calls. If another SMI
occurs while SMI is masked, the pending SMI is recog-
nized and executed on the next instruction boundary
after the current SMI completes. This instruction bound-
ary occurs before execution of the next instruction in the
interrupted application code, resulting in back-to-back
SMI handlers. Only one SMI signal can be pending while
SMI is masked. The SMI signal is synchronized inter-
nally and must be asserted at least three clock periods
prior to asserting the RDY signal to guarantee recogni-
tion on a specific instruction boundary. This is important
for servicing an I/O trap with an SMI handler.
SMI Active (SMIACT)
SMIACT indicates that the CPU is operating in SMM.
The CPU asserts SMIACT in response to an SMI inter-
rupt request on the SMI pin. SMIACT is driven active
after the CPU has completed all pending write cycles
Figure 4. Basic SMI Interrupt Service
SMI
#1
#2
#3
Instr
Instr
Instr
State Save
SMI Handler
State Restore
#4
#5
Instr
Instr
SMI
SMIACT
RSM
Figure 5. Basic SMI Hardware Interface
CPU
SMIACT
SMI
SMI Interface
}
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