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| 型號(hào)： | AM486 |
| 英文描述： | Am486 Microprocessor Software User＇s Manual? 4.40MB (PDF) |
| 中文描述： | Am486微處理器軟件用戶手冊(cè)？ 4.40MB（PDF格式） |
| 文件頁數(shù)： | 25/52頁 |
| 文件大小： | 1242K |
| 代理商： | AM486 |
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Am486DE2 Microprocessor
25
SMRAM State Save Map
When SMI is recognized on an instruction boundary, the
CPU core first sets the SMIACT signal Low, indicating to
the system logic that accesses are now being made to
the system-defined SMRAM areas. The CPU then
writes its state to the state save area in the SMRAM.
The state save area starts at SMBASE + [8000h +
7FFFh]. The default CS Base is 30000h; therefore, the
default state save area is at 3FFFFh. In this case, the
CS Base is also referred to as the SMBASE.
If the SMBASE relocation feature is enabled, the
SMRAM addresses can change. The following formula
is used to determine the relocated addresses where the
context is saved: SMBASE + [8000h + Register Offset],
where the default initial SMBASE is 30000h and the
Register Offset is listed in Table 3. Reserved spaces are
for new registers in future CPUs. Some registers in the
SMRAM state save area may be read and changed by
Figure 7. SMIACT Timing
CLK
CLK2
SMI
SMIACT
ADS
RDY
T1
T2
Normal State
State
Save
SMM
Handler
State
Restore
Normal
State
E
Clock-Doubled CPU
2 CLKs minimum
20 CLKs minimum
139 CLKs
User-determined
236 CLKs
2 CLKs minimum
20 CLKs minimum
A: Last RDY from non-SMM transfer to SMIACT assertion
B: SMIACT assertion to first ADS for SMM state save
C: SMM state save (dependent on memory performance)
D: SMI handler
E: SMM state restore (dependent on memory performance)
F: Last RDY from SMM transfer to deassertion of SMIACT
G: SMIACT deassertion of first non-SMM ADS
S S
S S
SS
SS
SS
SS
S S
SS
D
C
A
B
G
F
Figure 8. Redirecting System Memory
Address to SMRAM
SMRAM
System memory
accesses redirected
to SMRAM
System memory
accesses not
redirected to SMRAM
CPU
accesses to
system
address
space used
for loading
SMRAM
Normal
Memory
Space
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| AM486DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX - Am486DX Block Diagram |
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