參數(shù)資料
型號(hào)： AM50DL9608G
英文描述： 90NS, SOIC, IND TEMP(EEPROM)
中文描述： 64兆（4米× 16位）和32Mb（2米× 16位）和8兆（為512k × 16位），偽靜態(tài)存儲(chǔ)器（初步）
文件頁(yè)數(shù)： 64/70頁(yè)
文件大?。?/td> 1042K
代理商： AM50DL9608G
May 19, 2003
Am50DL9608G
63
P R E L I M I N A R Y
PSEUDO SRAM AC CHARACTERISTICS
Notes:
1. CE1#s controlled.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 31.
Pseudo SRAM Write Cycle—CE1#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out
High-Z
High-Z
t
WC
CE1#s
CE2s
t
AW
t
AS
(See Note 2 )
t
BW
t
(See Note 3)
t
WR
(See Note 4)
t
(See Note 5)
t
DW
t
DH
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