參數(shù)資料
型號(hào): AM50DL9608G
英文描述: 90NS, SOIC, IND TEMP(EEPROM)
中文描述: 64兆(4米× 16位)和32Mb(2米× 16位)和8兆(為512k × 16位),偽靜態(tài)存儲(chǔ)器(初步)
文件頁(yè)數(shù): 9/70頁(yè)
文件大小: 1042K
代理商: AM50DL9608G
8
Am50DL9608G
May 19, 2003
P R E L I M I N A R Y
PIN DESCRIPTION
A18–A0
= 19 Address Inputs (Common)
A21–A19, A-1 = 4 Address Inputs (Flash)
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f1
= Flash Chip Enable 1
(Am29DL640G)
CE#f2
= Flash Chip Enable 2
(Am29DL320G)
CE#1s
= Pseudo SRAM Chip Enable 1
CE2s
= Pseudo SRAM Chip Enable 2
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (Pseudo SRAM)
LB#s
= Lower Byte Control (Pseudo SRAM)
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CC
s
V
SS
NC
= Pseudo SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
19
16
DQ15–DQ0
A18–A0
CE#f1
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
A21–A19
LB#s
CE1#s
CE2s
CE#f2
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