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參數(shù)資料
| 型號： | Am53CF96KCW |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced SCSI-2 Controller (ESC) |
| 中文描述： | 增強(qiáng)型SCSI - 2控制器（調(diào)速器） |
| 文件頁數(shù)： | 25/76頁 |
| 文件大?。?/td> | 735K |
| 代理商： | AM53CF96KCW |
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P R E L I M I N A R Y
AMD
25
Am53CF94/Am53CF96
Target Select without
ATN
Steps
Internal State
Register (06H)
Bits 2:0 (Hex)
2
1
Interrupt Status
Register (05H)
Bits 7:0 (Hex)
11
11
Explanation
Selected; received entire CDB; check group code valid bit
Sequence halted in command phase due to parity error; some CDB bytes may
not have been received; check FIFO flags; Initiator asserted
ATN
in command
phase
Selected; received entire CDB; check group code valid bit
Sequence halted in command phase because of parity error; some CDB bytes
may not have been received; check FIFO flags
Selected; loaded bus ID into FIFO; null-byte message loaded into FIFO
2
1
01
01
0
01
Target Select with
ATN
Steps, SCSI-2 Bit NOT SET
Internal State
Interrupt Status
Register (06H)
Register (05H)
Bits 2:0 (Hex)
Bits 7:0 (Hex)
2
12
Explanation
Selection complete; received one message byte and entire CDB; Initiator as-
serted
ATN
during command phase
Halted in command phase; parity error and
ATN
true
Selected with
ATN
; stored bus ID and one message byte; sequence halted be-
cause
ATN
remained true after first message byte
Selection completed; received one message byte and the entire CDB
Sequence halted in command phase because of parity error; some CDB bytes
not received; check group code valid bit and FIFO flags
Selected with
ATN
; stored bus ID and one message byte; sequence halted be-
cause of parity error or invalid ID message
1
0
12
12
2
1
02
02
0
02
Target Select with
ATN
Steps, SCSI-2 Bit SET
Internal State
Interrupt Status
Register (06H)
Register (05H)
Bits 2:0 (Hex)
Bits 7:0 (Hex)
6
5
4
2
Explanation
12
12
12
12
Selection completed; received three message bytes and entire CDB.
ATN
is true
Halted in command phase; parity error and
ATN
true
ATN
remained true after third message byte
Selection completed; Initiator deasserts
ATN
after receipt of one message byte;
entire CDB received.
ATN
asserted during command phase
Sequence halted during command phase because of parity error; one message
byte received; some bytes of CDB not received; parity error and
ATN
true
Selected with
ATN
; stored bus ID and one message byte; sequence halted be-
cause of parity error or invalid ID message;
ATN
is true
Selection completed; received three message bytes and the entire CDB
Received three message bytes then halted in command phase because of parity
error; some CDB bytes not received; check group code valid bit and FIFO flags
Parity error during second or third message byte
Selection completed; Initiator deasserts
ATN
after receipt of one message byte;
entire CDB received
Sequence halted during command phase because of parity error; one message
byte received; some bytes of CDB not received; check FIFO flags and group
code valid bit
Selected with
ATN
; stored bus ID and one message byte; sequence halted be-
cause of parity error or invalid ID message
1
12
0
12
6
5
02
02
4
2
02
02
1
02
0
02
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