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參數(shù)資料
| 型號(hào)： | AM70PDL127CDH |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| 中文描述： | 2 × 64兆位（8米× 16位）的CMOS 3.0伏特，只有頁(yè)面模式閃存數(shù)據(jù)存儲(chǔ)128兆位（8米× 16位）的CMOS |
| 文件頁(yè)數(shù)： | 40/127頁(yè) |
| 文件大?。?/td> | 849K |
| 代理商： | AM70PDL127CDH |
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38
Am70PDL127CDH/Am70PDL129CDH
November 24, 2003
A D V A N C E I N F O R M A T I O N
ences between the Persistent Sector Protection and
the Password Sector Protection Mode:
■
When the device is first powered on, or comes out
of a reset cycle, the PPB Lock bit set to the
locked
state
, rather than cleared to the unlocked state.
■
The only means to clear the PPB Lock bit is by writ-
ing a unique
64-bit Password
to the device.
The Password Sector Protection method is otherwise
identical to the Persistent Sector Protection method.
A 64-bit password is the only additional tool utilized in
this method.
Once the Password Mode Locking Bit is set, the pass-
word is permanently set with no means to read, pro-
gram, or erase it. The password is used to clear the
PPB Lock bit. The Password Unlock command must
be written to the flash, along with a password. The
flash device internally compares the given password
with the pre-programmed password. If they match, the
PPB Lock bit is cleared, and the PPBs can be altered.
If they do not match, the flash device does nothing.
There is a built-in 2 μs delay for each “password
check.” This delay is intended to thwart any efforts to
run a program that tries all possible combinations in
order to crack the password.
Password and Password Mode Locking Bit
In order to select the Password sector protection
scheme, the customer must first program the pass-
word. The password may be correlated to the unique
Electronic Serial Number (ESN) of the particular flash
device. Each ESN is different for every flash device;
therefore each password should be different for every
flash device. While programming in the password re-
gion, the customer may perform Password Verify oper-
ations.
Once the desired password is programmed in, the
customer must then set the Password Mode Locking
Bit. This operation achieves two objectives:
1. Permanently sets the device to operate using the
Password Protection Mode. It is not possible to re-
verse this function.
2. Disables all further commands to the password re-
gion. All program, and read operations are ignored.
Both of these objectives are important, and if not care-
fully considered, may lead to unrecoverable errors.
The user must be sure that the Password Protection
method is desired when setting the Password Mode
Locking Bit. More importantly, the user must be sure
that the password is correct when the Password Mode
Locking Bit is set. Due to the fact that read operations
are disabled, there is no means to verify what the
password is afterwards. If the password is lost after
setting the Password Mode Locking Bit, there will be
no way to clear the PPB Lock bit.
The Password Mode Locking Bit, once set, prevents
reading the 64-bit password on the DQ bus and further
password programming. The Password Mode Locking
Bit is not erasable. Once Password Mode Locking Bit
is programmed, the Persistent Sector Protection Lock-
ing Bit is disabled from programming, guaranteeing
that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory
space and is accessible through the use of the Pass-
word Program and Verify commands (see “Password
Verify Command”). The password function works in
conjunction with the Password Mode Locking Bit,
which when set, prevents the Password Verify com-
mand from reading the contents of the password on
the pins of the device.
Write Protect (WP#)
The Write Protect feature provides a hardware method
of protecting sectors 0, 1, 268, and 269 in PDL 127 or
in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129 with-
out using V
ID
. This function is provided by the WP# pin
and overrides the previously discussed High Voltage
Sector Protection method.
If the system asserts V
IL
on the WP#/ACC pin, the de-
vice disables program and erase functions in the two
outermost 4 Kword sectors on both ends of the flash
array independent of whether it was previously pro-
tected or unprotected.
If the system asserts V
IH
on the WP#/ACC pin, the de-
vice reverts to whether sectors 0, 1, 268, and 269 in
PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in
PDL 129 were last set to be protected or unprotected.
That is, sector protection or unprotection for these sec-
tors depends on whether they were last protected or
unprotected using the method described in High Volt-
age Sector Protection.
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile
bit that reflects the state of the Password Mode Lock-
ing Bit after power-up reset. If the Password Mode
Lock Bit is also set after a hardware reset (RESET#
asserted) or a power-up reset, the ONLY means for
clearing the PPB Lock Bit in Password Protection
Mode is to issue the Password Unlock command. Suc-
cessful execution of the Password Unlock command
clears the PPB Lock Bit, allowing for sector PPBs
modifications. Asserting RESET#, taking the device
through a power-on reset, or issuing the PPB Lock Bit
Set command sets the PPB Lock Bit to a “1” when the
Password Mode Lock Bit is not set.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am70PDL127CDH66IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL127CDH66IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL127CDH85IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL127CDH85IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL129CDH | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM70PDL127CDH66I | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH66IS | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH66IT | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85I | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85IS | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
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