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參數(shù)資料
| 型號： | AM70PDL127CDH |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| 中文描述： | 2 × 64兆位（8米× 16位）的CMOS 3.0伏特，只有頁面模式閃存數(shù)據(jù)存儲128兆位（8米× 16位）的CMOS |
| 文件頁數(shù)： | 9/127頁 |
| 文件大?。?/td> | 849K |
| 代理商： | AM70PDL127CDH |
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November 24, 2003
Am70PDL127CDH/Am70PDL129CDH
7
A D V A N C E I N F O R M A T I O N
Hardware Reset (RESET#) ....................................................63
Figure 12. Reset Timings................................................................ 63
Erase and Program Operations ..............................................64
Figure 13. Program Operation Timings........................................... 65
Figure 14. Accelerated Program Timing Diagram........................... 65
Figure 15. Chip/Sector Erase Operation Timings ........................... 66
Figure 16. Back-to-back Read/Write Cycle Timings ....................... 67
Figure 17. Data# Polling Timings (During Embedded Algorithms).. 67
Figure 18. Toggle Bit Timings (During Embedded Algorithms)....... 68
Figure 19. DQ2 vs. DQ6.................................................................. 68
Temporary Sector Unprotect ..................................................69
Figure 20. Temporary Sector Unprotect Timing Diagram............... 69
Figure 21. Sector/Sector Block Protect and
Unprotect Timing Diagram.............................................................. 70
Alternate CE#f1 Controlled Erase and Program Operations ..71
Figure 22. Flash Alternate CE#f1 Controlled Write (Erase/Program)
Operation Timings........................................................................... 72
PSRAM AC Characteristics . . . . . . . . . . . . . . . . . 73
CE#s Timing ...........................................................................73
Figure 23. Timing Diagram for Alternating
Between Pseudo SRAM to Flash.................................................... 73
Figure 24. Timing Waveform of Power-up ...................................... 73
pSRAM AC CHaracteristics . . . . . . . . . . . . . . . . . 74
Functional Description ............................................................74
Absolute Maximum Ratings ....................................................74
Figure 25. Standby Mode State Machines...................................... 75
Standby Mode Characteristic .................................................75
AC Characteristics (VCC= 2.7-3.1 V, TA= -40 to 85×C) .........75
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 26. Timing Waveform of Read Cycle 1................................ 76
Figure 27. Timing Waveform of Read Cycle 2................................ 76
Figure 28. Timing Waveform of Write Cycle 1 ................................ 77
Figure 29. Timing Waveform of Write Cycle 2 ................................ 77
Figure 30. Timing Waveform of Write Cycle 3 ................................ 78
Erase And Programming Performance . . . . . . . .79
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 79
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 79
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 79
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .81
Table 1. Device Bus Operations .....................................................81
Requirements for Reading Array Data ...................................81
Page Mode Read ................................................................82
Writing Commands/Command Sequences ............................82
Write Buffer .........................................................................82
Accelerated Program Operation ..........................................82
Autoselect Functions ...........................................................82
Standby Mode ........................................................................ 82
Automatic Sleep Mode ...........................................................82
RESET#: Hardware Reset Pin ...............................................83
Output Disable Mode ..............................................................83
Table 2. Sector Address Table ........................................................84
Sector Group Protection and Unprotection .............................87
Table 3. Sector Group Protection/Unprotection Address Table .....87
Write Protect (WP#) ................................................................ 88
Temporary Sector Group Unprotect .......................................88
Figure 1. Temporary Sector Group Unprotect Operation................ 88
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 89
SecSi (Secured Silicon) Sector Flash Memory Region ..........90
Table 4. SecSi Sector Contents ......................................................90
Figure 3. SecSi Sector Protect Verify.............................................. 90
Hardware Data Protection ......................................................90
Low VCC Write Inhibit .........................................................91
Write Pulse “Glitch” Protection ............................................91
Logical Inhibit .......................................................................91
Power-Up Write Inhibit .........................................................91
Common Flash Memory Interface (CFI) . . . . . . . 91
Command Definitions. . . . . . . . . . . . . . . . . . . . . . 94
Reading Array Data ................................................................94
Reset Command .....................................................................95
Autoselect Command Sequence ............................................95
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..95
Word Program Command Sequence ......................................95
Unlock Bypass Command Sequence ..................................96
Write Buffer Programming ...................................................96
Accelerated Program ...........................................................97
Figure 4. Write Buffer Programming Operation.............................. 98
Figure 5. Program Operation ......................................................... 99
Program Suspend/Program Resume Command Sequence ...99
Figure 6. Program Suspend/Program Resume............................ 100
Chip Erase Command Sequence .........................................100
Sector Erase Command Sequence ......................................100
Figure 7. Erase Operation............................................................ 101
Erase Suspend/Erase Resume Commands .........................101
Command Definitions ........................................................... 102
Write Operation Status . . . . . . . . . . . . . . . . . . . 103
DQ7: Data# Polling ...............................................................103
Figure 8. Data# Polling Algorithm ................................................ 103
RY/BY#: Ready/Busy# .......................................................... 104
DQ6: Toggle Bit I ..................................................................104
Figure 9. Toggle Bit Algorithm...................................................... 105
DQ2: Toggle Bit II .................................................................105
Reading Toggle Bits DQ6/DQ2 .............................................105
DQ5: Exceeded Timing Limits ..............................................106
DQ3: Sector Erase Timer .....................................................106
DQ1: Write-to-Buffer Abort ...................................................106
Table 10. Write Operation Status ................................................. 106
Figure 10. Maximum Negative Overshoot Waveform................. 107
Figure 11. Maximum Positive Overshoot Waveform................... 107
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 108
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 12. Test Setup.................................................................. 109
Table 11. Test Specifications ....................................................... 109
Key to Switching Waveforms. . . . . . . . . . . . . . . 109
Figure 13. Input Waveforms and
Measurement Levels.................................................................... 109
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 110
Read-Only Operations .........................................................110
Figure 14. Read Operation Timings............................................. 110
Figure 15. Page Read Timings .................................................... 111
Hardware Reset (RESET#) ..................................................112
Figure 16. Reset Timings............................................................. 112
Erase and Program Operations ............................................113
Figure 17. Program Operation Timings........................................ 114
Figure 18. Accelerated Program Timing Diagram........................ 114
Figure 19. Chip/Sector Erase Operation Timings ........................ 115
Figure 20. Data# Polling Timings (During Embedded Algorithms) 116
Figure 21. Toggle Bit Timings (During Embedded Algorithms).... 117
Figure 22. DQ2 vs. DQ6............................................................... 117
Temporary Sector Unprotect ................................................118
Figure 23. Temporary Sector Group Unprotect Timing Diagram. 118
相關PDF資料 |
PDF描述 |
|---|---|
| Am70PDL127CDH66IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL127CDH66IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL127CDH85IS | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL127CDH85IT | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
| Am70PDL129CDH | 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM70PDL127CDH66I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH66IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH66IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
| AM70PDL127CDH85IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) |
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