參數(shù)資料
型號: AM79C901AJCT
廠商: ADVANCED MICRO DEVICES INC
元件分類: 網絡接口
英文描述: HomePHY Single-Chip 1/10 Mbps Home Networking PHY
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQCC68
封裝: PLASTIC, MO-047BAE, LCC-68
文件頁數(shù): 81/90頁
文件大?。?/td> 714K
代理商: AM79C901AJCT
Am79C901A
81
P R E L I M I N A R Y
AC CHARACTERISTICS (CONTINUED)
1 Mbps HomePNA Clock Timing (MII)
Note:
During AID interval, RX_CLK and TX_CLK stop for up to 140
μ
s.
Figure 15.
1 Mbps HomePNA Clock Timing (MII)
No.
Symbol
Parameter Description
Clock Period
Unit
Idle (excluding IPG time)
74
t
PER
TX_CLK, RX_CLK period
2333.34
ns
75
t
PWH
TX_CLK, RX_CLK pulse width HIGH
1165
ns
76
t
PWL
TX_CLK, RX_CLK pulse width LOW
1168
ns
Preamble (first 64 bits of TX MAC frame)
74
t
PER
TX_CLK, RX_CLK period
933.33
ns
75
t
PWH
TX_CLK, RX_CLK pulse width HIGH
466
ns
76
t
PWL
TX_CLK, RX_CLK pulse width LOW
467
ns
Data (throughout the data phase)
74
t
PER
TX_CLK, RX_CLK period
933 ns - 40
μ
s
75
t
PWH
TX_CLK, RX_CLK pulse width HIGH
466 ns - 40
μ
s
76
t
PWL
TX_CLK, RX_CLK pulse width LOW
467 ns - 40
μ
s
IPG (96 bit times following CRS falling edge)
74
t
PER
TX_CLK, RX_CLK period
933.33
ns
75
t
PWH
TX_CLK, RX_CLK pulse width HIGH
466
ns
76
t
PWL
TX_CLK, RX_CLK pulse width LOW
467
ns
TX_CLK,
RX_CLK
74
76
75
22304B-39
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AM79C901AJI HomePHY Single-Chip 1/10 Mbps Home Networking PHY
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相關代理商/技術參數(shù)
參數(shù)描述
AM79C901AJI 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:HomePHY Single-Chip 1/10 Mbps Home Networking PHY
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AM79C901AVC\\W 制造商:Advanced Micro Devices 功能描述: