- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C90 (Advanced Micro Devices, Inc.) CMOS Local Area Network Controller for Ethernet (C-LANCE) PDF資料下載
參數(shù)資料
| 型號： | AM79C90 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| 中文描述： | 的CMOS局域網(wǎng)控制器（丙應(yīng)聘以太網(wǎng)） |
| 文件頁數(shù)： | 21/62頁 |
| 文件大小： | 437K |
| 代理商： | AM79C90 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
P R E L I M I N A R Y
AMD
21
Am79C90
Bit
Name
Description
11
MERR
MEMORY ERROR is set when the
C-LANCE is the Bus Master and has
not received
READY
within 25.6
μ
s
after asserting the address on the
DAL lines.
When a Memory Error is detected,
the receiver and transmitter are
turned off (CSR
0
, TXON = 0, RXON
= 0) and an interrupt is generated if
INEA = 1.
MERR is READ/CLEAR ONLY, and
is set by the C-LANCE and cleared
by writing a “1” into the bit. Writing a
“0” has no effect. It is cleared by
RESET
or by setting the STOP bit.
RECEIVER INTERRUPT is set
when the C-LANCE updates an en-
try in the Receive Descriptor Ring for
the last buffer received or reception
is stopped due to a failure.
When RINT is set, an interrupt is
generated if INEA = 1.
RINT is READ/CLEAR ONLY, and is
set by the C-LANCE and cleared by
writing a “1” into the bit. Writing a “0”
has no effect. It is cleared by
RESET
or by setting the STOP bit.
TRANSMITTER INTERRUPT is set
when the C-LANCE updates an en-
try in the transmit descriptor ring for
the last buffer sent or transmission is
stopped due to a failure.
When TINT is set, an interrupt is
generated if INEA = 1.
TINT is READ/CLEAR ONLY and is
set by the C-LANCE and cleared by
writing a “1” into the bit. Writing a “0”
has no effect. It is cleared by
RESET
or by setting the STOP bit.
INITIALIZATION DONE indicates
that the C-LANCE has completed
the initialization procedure started
by setting the INIT bit. When IDON is
set, the C-LANCE has read the In-
itialization Block from memory and
stored the new parameters.
When IDON is set, an interrupt is
generated if INEA = 1.
10
RINT
09
TINT
08
IDON
IDON is READ/CLEAR ONLY, and is
set by the C-LANCE and cleared by
writing a “1” into the bit. Writing a “0”
has no effect. It is cleared by
RESET
or by setting the STOP bit.
Bit
Name
Description
07
INTR
INTERRUPT FLAG is set by the
“ORing” of BABL, MISS, MERR,
RINT, TINT and IDON. If INEA = 1
and INTR = 1, the
INTR
pin will be
LOW.
INTR is READ ONLY; writing this bit
has no effect. INTR is cleared by
RESET, by setting the STOP bit, or
by clearing the condition causing the
interrupt.
INTERRUPT ENABLE allows the
INTR
pin to be driven LOW when the
Interrupt Flag is set. If INEA = 1 and
INTR = 1, the
INTR
pin will be Low. If
INEA = 0, the
INTR
pin will be HIGH,
regardless of the state of the Inter-
rupt Flag.
INEA is READ/WRITE and cleared
by RESET or by setting the STOP
bit.
INEA can be set at any time, regard-
less of the state of the STOP bit.
(reference Appendix B).
RECEIVER ON indicates that the re-
ceiver is enabled. RXON is set when
STRT is set if DRX = 0 in the MODE
register in the initialization block and
the initialization block has been read
by the C-LANCE by setting the INIT
bit. RXON is cleared when IDON is
set from setting the INIT bit and DRX
= 1 in the MODE register, or a mem-
ory error (MERR) has occurred.
RXON is READ ONLY; writing this
bit has no effect. RXON is cleared by
RESET
or by setting the STOP bit.
TRANSMITTER ON indicates that
the transmitter is enabled. TXON is
set when STRT is set if DTX = 0 in
the MODE register in the initializa-
tion block and the INIT bit has been
set. TXON is cleared when IDON is
set and DTX = 1 in the MODE regis-
ter, or an error, such as MERR,
UFLO or BUFF, has occurred during
transmission.
TXON is READ ONLY; writing this bit
has no effect. TXON is cleared by
RESET
or by setting the STOP bit.
06
INEA
05
RXON
04
TXON
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C90JC | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| AM79C90JCTR | KPTC6CG10-6P |
| AM79C90PC | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| AM79C90PCTR | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| AM79C930 | PCnet-Mobile Single-Chip Wireless LAN Media Access Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C900 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| AM79C900AJC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C900JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C901 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AMD’s Am79C901 HomePNA-Compliant Device with Motorola’s MC68360. MPC860. MPC850. and MPC8260? - (PDF) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。