參數(shù)資料
型號(hào)： AM79C90JC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： CMOS Local Area Network Controller for Ethernet (C-LANCE)
中文描述： 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 60/62頁(yè)
文件大小： 437K
代理商： AM79C90JC
60
Am79C90
10. ALE Behavior
The LANCE device may drive the ALE pin LOW at the
end of each bus mastership period when ACON = 1
(ALE/AS active low—AS mode). When the bus master-
ship period ends, the ALE pin is tri-stated; hence, if
ALE is pulled HIGH by external logic, a glitch on ALE
results. The glitch occurs about when the LANCE de-
vice is releasing the bus by bringing HOLD high. The
C-LANCE device incorporates redesigned ALE logic to
prevent this glitch from occurring.
However, in the C-LANCE, when ACON = 0 (active
high ALE), ALE is driven high before it is tri-stated at
the end of every bus mastership period. In the LANCE,
when ACON = 0 (active high ALE), ALE is not driven
high before it is tri-stated at the end of every bus mas-
tership period.
This difference will not cause any problems in designs
that set ACON = 1 (AS; active low ALE). It
problems in designs in which ACON = 0. The ALE sig-
nal is intended to provide a strobe signal for an external
address latch. The rising edge, coupled with a subse-
quent falling edge that will occur if the pin is externally
pulled down, will cause an invalid address to be
strobed into the external address latch. However, since
this occurs at the end of the bus mastership period, and
further master cycles are not performed by the
C-LANCE subsequent to the invalid address being
strobed (until the next bus mastership period), the in-
valid address generally has no effect. A design could
have problems with this if external logic is continuously
decoding the latched address and taking some action
on it even though the C-LANCE is not executing any
master cycles.
could
cause
11. External Loopback on a Live Network
The LANCE device has an erratum that causes loop-
back failures when external loopback is run on a live
network. This erratum is fixed in the C-LANCE device.
12. Software Reset (STOP Bit) Handling
a. Latching of the STOP bit: In the LANCE device, writ-
ing the STOP bit in CSR0 causes all bus signals to
immediately float. With READY pulled up externally
(READY is open drain), this causes READY to deas-
sert prematurely during the Slave cycle. If DAS and
CS remain active, the LANCE device can errone-
ously start another Slave cycle. The C-LANCE de-
vice latches the STOP bit and, when it is set, allows
the Slave cycle in progress to complete before re-
setting the part.
b. Preservation of CSR1 and CSR2: The LANCE de-
vice does not preserve the contents of CSR1 and
CSR2 during the initialization process. Hence,
when the STOP bit is set, the contents of CSR1 and
CSR2 are not the same as they were before initial-
ization and they must be rewritten before
re-initializing. This is not really a problem in the
LANCE device, but it can add extra instructions to
software. The C-LANCE device removes this soft-
ware burden by preserving the contents of CSR1
and CSR2 during initialization so that when the
STOP bit is set, they do not have to be reloaded be-
fore re-initializing. Note, however, that if the default
values of CSR3 (defaults for BCON, ACON, and
BSWP are 0, 0, and 0, respectively) are not used,
CSR3 must still be reloaded after setting the STOP
bit in the C-LANCE device, since CSR3 is cleared
when the STOP bit is set.
13. CSR0 Slave Read Data Stability
In the LANCE device, the status bit latches in CSR0
may change at any time, as governed by the occur-
rence of the external events they monitor. Hence, the
ERR, BABL, CERR, MISS, IDON, and INTR bits in
CSR0 may change during a Slave read cycle in which
they are being accessed. This can cause timing viola-
tions on the DAL lines. In the C-LANCE device, CSR0
is latched in a shadow register during a read so that
timing on the DAL lines is guaranteed.
14. INEA Bit Behavior
With the C-LANCE device, an INEA bit can be set in
CSR0 at any time, regardless of the state of the STOP
bit. This actually removes a restriction that was present
in the LANCE device, in which the INEA bit in CSR0
could be not be set while the STOP bit was set.
This difference between the two devices does not affect
normal device operation, but could disrupt diagnostic
code written for the LANCE device.
15. Effect of Setting the STOP Bit on CSR0 Bits
In the LANCE device, CSR0 is reset when the STOP bit
in CSR0 is set.
This reset happens even if the STOP
bit was already set.
When the reset occurs, all of the
other bits in CSR0 are cleared. In the C-LANCE, CSR0
is reset when the STOP bit is set in CSR0
STOP bit was not already set.
only if the
This difference between the two devices does not affect
normal device operation, but could disrupt diagnostic
code written for the LANCE device.
16. AC Specification Changes
The following differences in AC specification exist
between the C-LANCE and the LANCE.
C-LANCE
LANCE
#06 (t
TEP
) maximum
60 ns
70 ns
#08 (t
TDP
) maximum
60 ns
70 ns
#18 (t
RDS
) minimum
35 ns
40 ns
#30 (t
RDAS
) minimum
40 ns
50 ns
#45 (t
RDYS
) minimum
65 ns
75 ns
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參數(shù)描述
AM79C90JC-G 制造商:Rochester Electronics LLC 功能描述:
AM79C90JCTR 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:CMOS Local Area Network Controller for Ethernet (C-LANCE)
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AM79C90PCB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C90PCTR 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:CMOS Local Area Network Controller for Ethernet (C-LANCE)
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