參數(shù)資料
型號(hào): AM79C975KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述: 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁(yè)數(shù): 138/304頁(yè)
文件大小: 2092K
代理商: AM79C975KCW
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138
Am79C973/Am79C975
P R E L I M I N A R Y
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PADR[47:32]Physical
Address
Register,
PADR[47:32].The contents of
this register are loaded from EE-
PROM after H_RESET or by an
EEPROM
read
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
command
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR15: Mode
This register
s fields are loaded during the Am79C973/
Am79C975 controller initialization routine with the cor-
responding Initialization Block values, or when a direct
register write has been performed on this register.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
PROM
Promiscuous
PROM = 1, all incoming receive
frames are accepted.
Mode.
When
Read/Write accessible only when
either the STOP or the SPND bit
is set.
14
DRCVBC
Disable
When
Am79C973/Am79C975 controller
from receiving broadcast mes-
sages. Used for protocols that do
not support broadcast address-
ing, except as a function of multi-
cast. DRCVBC is cleared by
activation
of
S_RESET (broadcast messages
will be received) and is unaffect-
ed by STOP.
Receive
set,
Broadcast.
disables
the
H_RESET
or
Read/Write accessible only when
either the STOP or the SPND bit
is set.
13
DRCVPA
Disable Receive Physical Ad-
dress. When set, the physical ad-
dress detection (Station or node
ID) of the Am79C973/Am79C975
controller
will
Frames addressed to the nodes
individual physical address will
not be recognized.
be
disabled.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
12-9
RES
Reserved locations. Written as
zeros and read as undefined.
8-7 PORTSEL[1:0] Port Select bits allow for software
controlled selection of the net-
work medium. The only legal val-
ues for this field is 11.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Cleared by H_RESET or
S_RESET and is unaffected by
STOP.
6
INTL
Internal Loopback. See the de-
scription of LOOP (CSR15, bit 2).
Read/Write accessible only when
either the STOP or the SPND bit
is set.
5
DRTY
Disable Retry. When DRTY is set
to 1, the Am79C973/Am79C975
controller will attempt only one
transmission. In this mode, the
device will not protect the first 64
bytes of frame data in the Trans-
mit FIFO from being overwritten,
because automatic retransmis-
sion will not be necessary. When
DRTY is set to 0, the Am79C973/
Am79C975 controller will attempt
16 transmissions before signal-
ing a retry error.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
4
FCOLL
Force Collision. This bit allows
the collision logic to be tested.
The Am79C973/Am79C975 con-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C975VCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
AM79C976 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KC 制造商:Rochester Electronics LLC 功能描述:METRIC PLASTIC QUAD-RING - Bulk
AM79C976KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
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