參數(shù)資料
型號(hào): AM79C985KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: enhanced Integrated Multiport Repeater Plus (eIMR+⑩)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 23/48頁(yè)
文件大?。?/td> 260K
代理商: AM79C985KCW
Am79C985
23
P R E L I M I N A R Y
When two eIMR+ devices are connected to one HIMIB
device, the secondary device transmits the status of its
TP ports, then transmits the status of the primary eIMR+
TP ports and AUI port (CRS and CI). Note that the sec-
ondary device does not transmit the status of its AUI
port. At Reset, the secondary device (and single eIMR+
device) internally synchronizes the CRS stream to begin
with the AUI CI bit. SO is the eIMR+ device response to
a Get command.
The pins SI_D and CRS_I are multi-purpose pins. Their
primary purpose is management input to the primary
eIMR+ device. They are also used to set the manage-
ment mode of the eIMR+ device. The mode is set on the
rising edge of RST. The settings are shown in Table 4.
Following reset, the eIMR+ devices retain their manage-
ment designations. However, CRS_I and SI_D return to
their management port functions.
Command/Response Timing
Figure 7 shows the command/response timing. At the
end of a GET command, the eIMR+ device waits two
SCLK cycles and then transmits the response on SO.
The secondary eIMR+ device stores the data received
on the SI_D input (from the primary eIMR+ device) in
an internal register. When it has transmitted D3 data, it
appends the received response to the end of the SO
signal.
Following reset, after the eIMR+ devices have been as-
signed their primary and secondary designation, SO
and SI_D return to their management-port functions.
Port Activity
In addition to providing a means for receiving com-
mands and sending data in response to those com-
mands, the management port includes a CRS signal
that transmits the state of the eIMR+ device’s internal
carrier-sense signals.
When two eIMR+ devices are connected to one
Am79C987 HIMIB device (as shown in the System
Applications section), CRS_I of the secondary device
receives the following signals from the primary device:
the carrier-sense signals of the AUI port, the CI-bit sta-
tus of the AUI port, and the carrier-sense signals of the
TP ports. The secondary device transmits the status of
the AUI port (CRS and CI) for the primary device, the
status of its own TP ports (TP0-TP3), and then the sta-
tus of the primary device’s TP ports (TP4-TP7). The
status of the AUI port of the secondary device is not
retransmitted (see Figure 8).
Figure 7. Management Get Command/Response
Table 4. eIMR+ Device Management Designations
Two eIMR+ Devices
CRS_I
0
0
1
1
SI_D
0
1
0
1
Single eIMR+ Device
Primary eIMR+ Device
Secondary eIMR+ Device
Note:
For SO on the Primary device, D[3:0] corresponds to TP[7:4].
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3
SCLK
SI
SO
Primary eIMR+ Device or
Single eIMR+ Device
ST D0 D1 D2 D3 D4 D5 D6 D7
SO
Secondary eIMR+ Device
20651B-12
相關(guān)PDF資料
PDF描述
AM79C987 Hardware Implemented Management Information Base (HIMIB) Device
AM79C987JC Hardware Implemented Management Information Base (HIMIB) Device
AM79C987JCB Hardware Implemented Management Information Base (HIMIB) Device
AM79C988A IC,Motor Controller,CMOS,SOP,8PIN
AM79C988 Quad Integrated Ethernet Transceiver (QuIET⑩)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C985WW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C987 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Hardware Implemented Management Information Base (HIMIB) Device
AM79C987JC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Hardware Implemented Management Information Base (HIMIB) Device
AM79C987JCB 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Hardware Implemented Management Information Base (HIMIB) Device