參數(shù)資料
型號: AMC1210
英文描述: Quad Digital Filter for 2nd-Order Delta-Sigma Modulator
中文描述: 四數(shù)字濾波器2階Δ-Σ調(diào)制器
文件頁數(shù): 17/47頁
文件大?。?/td> 805K
代理商: AMC1210
www.ti.com
Comparator Unit
An independent comparator unit allows the user to monitor input conditions with a fast settling time without
sacrificing input measurement resolution. The filter of the comparator unit is similar to the sinc filter unit, with
OSR values ranging continuously between 1 and 32. Setting the OSR to 32, a maximum 15-bit output width of
32,768 can be achieved. The output of the filter is compared with two programmed threshold levels to detect
over- and under-value conditions. These threshold levels are programmed in the high and low level
Threshold
Registers
for each individual filter module. When an over- or under-value condition occurs, it signals the interrupt
unit to set an interrupt signal and store the conditions in the
Interrupt Register
. The
Interrupt Register
can then
be polled to see which condition caused the interrupt signal. It is not possible to read out the value of the
comparator filter.
AMC1210
SBAS372A–APRIL 2006–REVISED OCTOBER 2006
The calibration mechanism follows this sequence:
1. The modulator data is sampled at the frequency of the system clock (CLK).
2. The number of CLK cycles between transitions is counted and recorded for 1024 consecutive transitions.
3. The resulting array will have a '1' in the bit location that corresponds to the number of CLK cycles counted
between transitions. For example, the sequence shown in
Table 8
means that there was at least one
instance where three and four, as well as seven and eight, CLK cycles occurred between two transitions.
This array is stored in the bits MS10–MS0 in the
Control Parameter Register
.
4. An algorithm looks for a group of zeros that has ones before and after it. If this pattern is not found, the bits
MALx and MAFx in the
Status Register
are set high.
5. If the algorithm is successful, it will use the location of the first '0' as the number of CLK cycles needed to
determine the frequency and which transitions are valid in the Manchester code.
6. The algorithm starts over from Step 2 automatically.
Table 8. Example Control Parameter Register
0
1
1
MS8
MS7
MS6
9
8
7
VALUE
BIT
CLK CYCLES
0
0
0
0
1
1
0
0
MS10
11
MS9
10
MS5
6
MS4
5
MS3
4
MS2
3
MS1
2
MS0
1
The MALx bit shows the status of the previous Manchester decoder calibration cycle. If it is high, the decoder
calibration has failed on the previous calibration cycle. The MAFx bit shows if any failures have occurred since
the last read of the
Status Register
. Any MALx failure will cause MAFx to go high. MAFx is reset to low when the
Status Register
is read.
The decoding procedure is performed continuously when the AMC1210 is configured for Modulator Mode 2.
Note that the CLK frequency must be at least six times the Manchester data rate for the decoder to perform
properly.
This filter, together with the comparators, is generally used to detect over-currents. It is necessary to decide on
an OSR given the desired resolution/settling time combination. This programming will be discussed in more
detail in the Applications Information section.
The comparator filter unit and the sinc filter unit differ in the way they handle input data. The comparator filter
unit translates a low input signal to a '0' and a high input signal to a '1', whereas the sinc filter unit uses '–1' and
'1'. The resulting calculations give only positive values for the output of the comparator filter. The data
representation is straight binary.
Table 9
and
Figure 14
show the different full-scale values that the comparator
filter can store using different oversampling ratios.
Table 9. Peak Data Values for Different OSR/Filter Combinations
OSR
x
4
8
16
32
Sinc
1
0 to x
0 to 4
0 to 8
0 to 16
0 to 32
Sinc
2
0 to x
2
0 to 16
0 to 64
0 to 256
0 to 1024
Sinc
3
0 to x
3
0 to 64
0 to 512
0 to 4096
0 to 32,768
Sincfast
0 to 2x
2
0 to 32
0 to 128
0 to 512
0 to 2048
17
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