The CHIP_CLK and fCLK ar" />
參數(shù)資料
型號(hào)： AMIS49587C5871RG
廠商： ON Semiconductor
文件頁數(shù)： 14/55頁
文件大?。?/td> 0K
描述： IC MODEM PLC 50/60MHZ 28PLCC
標(biāo)準(zhǔn)包裝： 750
波特率： 可選
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 帶卷 (TR)
AMIS49587
http://onsemi.com
21
6.1.4 Clock Generator and Timer
The CHIP_CLK and fCLK are used to generate a number
of timing signals used for the synchronization and interrupt
generation. The timing generation has a fixed repetition rate
which corresponds to the length of a physical subframe. (see
paragraph Send and Receive network data).
The timing generator is the same for transmit and receive
mode. When AMIS49587 switches from receive to
transmit and back from transmit to receive, the
R_CHIP_CNT counter value is maintained. As a result all
timing signals for receive and transmit have the same
relative timing. The following timing signals are defined as:
BIT_CLK
63
64
65
2871 2872
1
0
2879
2
3
4
5
6
7
8
9
CHIP_CLK
BYTE_CLK
FRAME_CLK
PRE_FRAME_CLK
PRE_BYTE_CLK
R_CHIP_CNT
PRE_SLOT
Start of the physical subframe
Figure 16. Timing Signals
CHIP_CLK is the output of the PLL and 8 times the bit rate on the physical interface. See also paragraph 50/60 Hz PLL
BIT_CLK is active at counter values 0,8,16, .. 2872 and inactive at all other counter values. This signal is used to indicate the
transmission of a new bit.
BYTE_CLK is active at counter values 0,64,128, .. 2816 and inactive at all other counter values. This signal is used to indicate
the transmission of a new byte.
FRAME_CLK is active at counter values 0 and inactive at all other counter values. This signal is used to indicate the
transmission or reception of a new frame.
PRE_BYTE_CLK is a signal which is 8 CHIP_CLK sooner than BYTE_CLK. This signal is used as an interrupt for the
internal microcontroller and indicates that a new byte for transmission must be generated.
PRE_FRAME_CLK is a signal which is 8 CHIP_CLK sooner than FRAME_CLK. This signal is used as an interrupt for the
internal microcontroller and indicates that a new frame will start at the next FRAME_CLK.
PRE_SLOT is logic 1 between the rising edge of PRE_FRAME_CLK and the rising edge of FRAME_CLK. This signal can
be provided at the digital output pin TX_DATA_PRE_SLOT when R_CONF[7] = 0 (See paragraph WriteConfigRequest, field
TX_DATA_PRESLOT_SEL) and can be used by the external host controller to synchronize its software with the
FRAME_CLK of AMIS49587.
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