參數(shù)資料
型號(hào): AMMP-6120
元件分類(lèi): 倍頻器
英文描述: 4000 MHz - 12000 MHz RF/MICROWAVE FREQUENCY DOUBLER
封裝: 5 X 5 MM, SURFACE MOUNT PACKAGE-8
文件頁(yè)數(shù): 5/6頁(yè)
文件大?。?/td> 266K
代理商: AMMP-6120
-30
-25
-20
-15
-10
-5
0
4
6
8
1012 1416 1820 2224 26
Frequncy (GHz)
I/P
&
O
/P
R
e
tu
rn
L
o
s
(
d
B
)
S11
S22
Fig. 17 Input and Output Return Loss
Biasing and Operation
This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Agilent Technologies releases this product
for general sales, Agilent Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability
of the product(s) at anytime.
Revision Date: 4/28/04
Revision Number: 5.0
Fig. 18 Top Level Schematic of Frequency doubler
The frequency doubler MMIC consists of an active balun. The
outputs of this balun feed the gates of balanced FETs and the
drains are connected to form the single-ended output. This
results in fundamental frequency & odd harmonics cancellation.
The even harmonic drain currents are in phase and so added in
phase. Node ‘S’ acts as a virtual ground. Input matching
networks (M/N) is designed to provide good match at
fundamental frequency and produces high impedance mismatch
to higher harmonics.
AMMP-6120 is biased with a single positive drain supply and
single negative gate supply using separate bypass capacitors. It
is normally biased with the drain supply connected to the VDD
bond pad and the gate supply connected to the Vgg bond pad.
For most of the application it is recommended to use a Vg =-
1.2V to -1.4V and Vd=4.5V to 5.0V.
The AMMP-6120 performance changes with Drain
(Vd) and Gate bias (Vg) as shown in the previous
graphs. Improvements in performance are possible
for output power or fundamental suppression by
optimizing the Vg from -1.2V to -1.4V and/or Vd
from 4.5 to 5.0V.
The RF input and output port are AC coupled thus
no DC voltage is present at either ports. No ground
wired are needed since ground connections are
made with plated through-holes to the backside of
the device.
Top level schematic of frequency is shown in fig.
18. The active balun circuit and output amplifier of
circuit are self biased. Negative bias (below pinch
off) is applied to FETs ‘F1’ and ‘F2’ only. FETs ‘F1’
and ‘F2’ has no significant contribution to total
drain current and so should not be adjusted to set
drain current. It should only be used to set output
power and fundamental & higher harmonics
suppression optimization of doubler.
S
M/N
@ fo
F1
Filter
@ 2fo
F2
Active
Balun
Amp
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