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參數(shù)資料
| 型號： | AMP374P6453BT1-C1H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs |
| 中文描述： | 64米× 72 SDRAM的內(nèi)存32兆的基礎(chǔ)上× 8，4銀行，8K的刷新，3.3同步DRAM，帶ECC |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 72K |
| 代理商： | AMP374P6453BT1-C1H |
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 6 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AC OPERATING TEST CONDITIONS
( V
DD
= 3.3V ± 0.3V, T
A
= 0 to 70
o
C)
Parameter
AC input levels
Input timing measurement reference level
Input rise and fall time
Output measurement reference level
Output load condition
Value
V
IH
/V
IL
= 2.4V / 0.4V
1.4V
tr / tf = 1ns / 1ns
1.4V
See Fig. 2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Refer to the individual component not the whole module.
Parameter
Symbol
Version
-1H
20
20
20
50
100
70
2
2CLK + 20 ns
1
1
1
1
Unit
Note
Row active to row active delay
RAS
to
CAS
delay
Row precharge time
Row active time
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency = 2
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
ea
1
1
1
1
Row cycle time
Last data in to row precharge
Last data in to active delay
Last data in to new col. add. delay
Last data in to burst stop
Column address to col. add. delay
Number of valid output data
1
2,5
5
2
2
3
4
Note : 1.
The minimum number of clock cycles is determined by dividing the minimum time
required with clock cycle time, and then rounding off to the next higher integer.
Minimum delay is required to complete write.
All parts allow every cycle column address change.
In case of row precharge interrupt, auto precharge and read burst stop.
For -80/1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported.
2.
3.
4.
5.
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