參數(shù)資料
型號(hào): AMP374P6453BT1C1H
廠商: Electronic Theatre Controls, Inc.
英文描述: 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs
中文描述: 64米× 72 SDRAM的內(nèi)存32兆的基礎(chǔ)上× 8,4銀行,8K的刷新,3.3同步DRAM,帶ECC
文件頁數(shù): 11/12頁
文件大?。?/td> 72K
代理商: AMP374P6453BT1C1H
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 11 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
SERIAL PRESENCE DETECT
Organization: 64M x 72
Composition: 32M x 8*18
# of rows in module: 2
# of banks in component: 4
Refresh: 8K/64ms
Byte#
Function Description
Function Supported
-1H
128 bytes
Hex Value
-1H
80h
Note
0
# of bytes written into serial memory at module
manufacturer
Total # of bytes of SPD memory devices
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module rows on this assembly
Data width of this assembly
Data width of this assembly
Voltage interface standard of this assembly
SDRAM cycle time @ CAS latency 3
SDRAM access time from clock @ CAS latency 3
DIMM configuration type
Refresh rate and type
Primary SDRAM width
Error checking SDRAM width
Minimum clock delay for back-to-back random column
address
SDRAM device attributes: Burst lengths supported
SDRAM device attributes: # of banks on SDRAM
device
SDRAM device attributes: CAS latency
SDRAM device attributes: CS latency
SDRAM device attributes: Write latency
SDRAM module attributes
1
2
3
4
5
6
7
8
9
256 bytes (2K-bit)
SDRAM
13
10
2
72 bits
-
LVTTL
10ns
6ns
ECC
7.8 μs, support self refresh
x8
x8
tCCD = 1CLK
08h
04h
0Dh
0Ah
02h
48h
00h
01h
A0h
60h
02h
82h
08h
08h
01h
1
1
2
2
10
11
12
13
14
15
16
17
1,2,4,8 & Full page
4 banks
8Fh
04h
18
19
20
21
2 & 3
0 CLK
0 CLK
06h
01h
01h
00h
Non-buffered, Non-
registered & redundant
addressing
±10% voltage tolerance,
Burst read, Single bit Write,
precharge all, auto
precharge
10ns
6ns
-
-
20ns
20ns
20ns
50ns
2 rows of 256MB
2ns
1ns
2ns
1ns
-
22
SDRAM device attributes: General
OEh
23
24
25
26
27
28
29
30
31
32
33
34
35
SDRAM cycle time @ CAS latency 2
SDRAM access time from clock @ CAS latency 2
SDRAM cycle time @ CAS latency 1
SDRAM access time from clock @ CAS latency 1
Minimum row precharge time (=tRP)
Minimum row active to row active delay(tRRD)
Minimum RAS to CAS delay (=tRCD)
Minimum activate precharge time(=tRAS)
Module row density
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
Data signal input hold time
Superset information (may be used in the future)
A0h
60h
00h
00h
14h
14h
14h
32h
40h
20h
10h
20h
10h
00h
2
2
36-61
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