ProASICPLUS Flash Family FPGAs v5.9 2-61 Synchronous Write and Read to the Same " />
參數(shù)資料
型號: APA600-FGG484
廠商: Microsemi SoC
文件頁數(shù): 148/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 600K 484-FBGA
標準包裝: 40
系列: ProASICPLUS
RAM 位總計: 129024
輸入/輸出數(shù): 370
門數(shù): 600000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
ProASICPLUS Flash Family FPGAs
v5.9
2-61
Synchronous Write and Read to the Same Location
Note: * New data is read if WCLKS
occurs before setup time. The data stored is read if WCLKS occurs after hold time. The plot shows
the normal operation status.
Figure 2-34 Synchronous Write and Read to the Same Location
Table 2-58 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
WCLKRCLKS
WCLKS
↑ to RCLKS ↑ setup time
0.1
ns
WCLKRCLKH
WCLKS
↑ to RCLKS ↑ hold time
7.0
ns
OCH
Old DO valid from RCLKS
3.0
ns
OCA/OCH displayed for
Access Timed Output
OCA
New DO valid from RCLKS
7.5
ns
Notes:
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write
clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS
and RCLKS driven by the same design signal.
3. If WCLKS changes after the hold time, the data will be read.
4. A setup or hold time violation will result in unknown output data.
RCLKS
DO
WCLKS
t
WCLKRCLKH
New Data*
Last Cycle Data
t
WCLKRCLKS
t
OCH
t
CCYC
t
CMH
t
CML
t
OCA
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