ProASICPLUS Flash Family FPGAs v5.9 2-7 Power-Up Sequencing Whi" />
參數(shù)資料
型號： APA750-FG676I
廠商： Microsemi SoC
文件頁數(shù)： 79/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 750K 676-FBGA
標準包裝： 40
系列： ProASICPLUS
RAM 位總計： 147456
輸入/輸出數(shù)： 454
門數(shù)： 750000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
ProASICPLUS Flash Family FPGAs
v5.9
2-7
Power-Up Sequencing
While ProASICPLUS devices are live at power-up, the order
of VDD and VDDP power-up is important during system
start-up. VDD should be powered up simultaneously with
VDDP on ProASIC
PLUS devices. Failure to follow these
guidelines may result in undesirable pin behavior during
system start-up. For more information, refer to Actel’s
note.
LVPECL Input Pads
In addition to standard I/O pads and power pads,
ProASICPLUS devices have a single LVPECL input pad on
both the east and west sides of the device, along with
AVDD and AGND pins to power the PLL block. The
LVPECL pad cell consists of an input buffer (containing a
low voltage differential amplifier) and a signal and its
complement, PPECL (I/P) (PECLN) and NPECL (PECLREF).
The LVPECL input pad cell differs from the standard I/O
cell in that it is operated from VDD only.
Since it is exclusively an input, it requires no output
signal, output enable signal, or output configuration
bits. As a special high-speed differential input, it also
does not require pull-ups. Recommended termination
for LVPECL inputs is shown in Figure 2-7. The LVPECL pad
cell compares voltages on the PPECL (I/P) pad (as
illustrated in Figure 2-8) and the NPECL pad and sends
the results to the global MUX (Figure 2-11 on page 2-11).
This high-speed, low-skew output essentially controls the
clock conditioning circuit.
LVPECLs are designed to meet LVPECL JEDEC receiver
standard levels (Table 2-5).
Figure 2-7 Recommended Termination for LVPECL Inputs
Figure 2-8 LVPECL High and Low Threshold Values
Table 2-5
LVPECL Receiver Specifications
Symbol
Parameter
Minimum
Maximum
Units
VIH
Input High Voltage
1.49
2.72
V
VIL
Input Low Voltage
0.86
2.125
V
VID
Differential Input Voltage
0.3
VDD
V
+
_
PPECL
NPECL
From LVPECL Driver
Data
Z = 50
Ω
0
Z = 50
Ω
0
R = 100
Ω
2.72
2.125
1.49
0.86
Voltage
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