ProASICPLUS Flash Family FPGAs 2- 8 v5.9 Boundary Scan (JTAG) P" />
參數(shù)資料
型號： APA750-FG676I
廠商： Microsemi SoC
文件頁數(shù)： 89/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 750K 676-FBGA
標準包裝： 40
系列： ProASICPLUS
RAM 位總計： 147456
輸入/輸出數(shù)： 454
門數(shù)： 750000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
ProASICPLUS Flash Family FPGAs
2- 8
v5.9
Boundary Scan (JTAG)
ProASICPLUS devices are compatible with IEEE Standard
1149.1, which defines a set of hardware architecture and
mechanisms for cost-effective, board-level testing. The
basic ProASICPLUS boundary-scan logic circuit is composed
of the TAP (test access port), TAP controller, test data
registers, and instruction register (Figure 2-9). This circuit
supports all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD
and
BYPASS)
and
the
optional
IDCODE instruction (Table 2-6).
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI and TDO
(test data input and output), TMS (test mode selector)
and TRST (test reset input). TMS, TDI and TRST are
equipped with pull-up resistors to ensure proper
operation when no input data is supplied to them. These
pins are dedicated for boundary-scan test usage. Actel
recommends that a nominal 20 k
Ω pull-up resistor is
added to TDO and TCK pins.
The TAP controller is a four-bit state machine (16 states)
that operates as shown in Figure 2-10 on page 2-9. The
1s and 0s represent the values that must be present at
TMS at a rising edge of TCK for the given state transition
to occur. IR and DR indicate that the instruction register
or the data register is operating in that state.
ProASICPLUS devices have to be programmed at least
once for complete boundary-scan functionality to be
available. Prior to being programmed, EXTEST is not
available. If boundary-scan functionality is required prior
to programming, refer to online technical support on the
Actel website and search for ProASICPLUS BSDL.
Figure 2-9 ProASICPLUS JTAG Boundary Scan Test Logic Circuit
Device
Logic
TDI
TCK
TMS
TRST
TDO
I/O
Bypass Register
Instruction
Register
TAP
Controller
Test Data
Registers
Table 2-6
Boundary-Scan Opcodes
Hex Opcode
EXTEST
00
SAMPLE/PRELOAD
01
IDCODE
0F
CLAMP
05
BYPASS
FF
Table 2-6
Boundary-Scan Opcodes
Hex Opcode
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