參數(shù)資料
型號： APW7066QAC-TRL
廠商： ANPEC ELECTRONICS CORP
元件分類： 穩(wěn)壓器
英文描述： Dual Synchronous Buck PWM Controllers and One Linear Controller
中文描述： SWITCHING CONTROLLER, QCC32
封裝： 5 X 5 MM, LEAD FREE, QFN-32
文件頁數(shù)： 17/33頁
文件大小： 338K
代理商： APW7066QAC-TRL
Copyright
ANPEC Electronics Corp.
Rev. A.7 - Mar., 2008
APW7066
24
Application Information
GAINLC
=
1
C
ESR
s
C
L
s
C
ESR
s
1
OUT
2
OUT
+
×
+
×
+
Linear Regulator Input/Output Capacitor Selec-
tion
The input capacitor is chosen based on its voltage
rating. Under load transient condition, the input
capacitor will momentarily supply the required
transient current. The output capacitor for the linear
regulator is chosen to minimize any droop during load
transient condition. In addition, the capacitor is chosen
based on its voltage rating.
Linear Regulator Input/Output MOSFET Selection
The maximum DRIVE3 voltage is determined by the
VCC12. Since this pin drives an external N-channel
MOSFET, therefore the maximum output voltage of
the linear regulator is dependent upon the VGS.
VOUT3MAX = VCC12 - VGS
Another criteria is its efficiency of heat removal. The
power dissipated by the MOSFET is given by:
Pdiss = Iout x (VIN - VOUT3)
where Iout is the maximum load current VOUT3 is the
nominal output voltage
In some applications, heatsink might be required to
help maintain the junction temperature of the MOSFET
below its maximum rating.
Linear Regulator Compensation Selection
The linear regulator is stable over all load current.
However, the transient response can be further
enhanced by connecting a RC network between the
FB3 and DRIVE3 pin. Depending on the output
capacitance and load current of the application, the
value of this RC network is then varied. A good starting
point for the resistor value is 6.8k
and 470pF for the
capacitor.
PWM Compensation
The output LC filter of a step down converter introduces
a double pole, which contributes with
–40dB/decade
gain slope and 180 degrees phase shift in the control
loop. A compensation network between COMP, FB
and VOUT should be added. The compensation
network is shown in Fig. 12.
The output LC filter consists of the output inductor
and output capacitors. The transfer function of the LC
filter is given by:
The poles and zero of this transfer function are:
FLC
=
OUT
C
L
2
1
×
π
×
FESR
=
OUT
C
ESR
2
1
×
π
×
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
L
COUT
ESR
Output
PHASE
Figure 9. The Output LC Filter
FESR
FLC
Frequency
-40dB/dec
-20dB/dec
Figure 10. The LC Filter Gain & Frequency
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