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| 型號： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數(shù)： | 39/120頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
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Instruction Set - MUL, MLA
35
4.6.2 CPSR ags
Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z
(Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if
the result is zero). The C (Carry) flag is set to a meaningless value and the V (oVerflow) flag is unaffected.
4.6.3 Instruction Cycle Times
The Multiply instructions take 1S +
m
I incremental cycles to execute, where S and I are as defined in section
5.1 Cycle types on page 65.
m
is the number of cycles required by the multiply algorithm, which is determined by the contents of
Rs. Multiplication by any number between
2^(2m-3)
and
2^(2m-1)-1
takes 1S+mI
m
cycles for
1<m>16
. Multiplication by 0 or 1 takes 1S+1I cycles, and multiplication by any number greater than
or equal to 2^(29) takes 1S+16I cycles. The maximum time for any multiply is thus 1S+16I cycles.
4.6.4 Assembler syntax
MUL{cond}{S} Rd,Rm,Rs
MLA{cond}{S} Rd,Rm,Rs,Rn
{cond} - two-character condition mnemonic, see
Figure 6: Condition Codes
{S} - set condition codes if S present
Rd, Rm, Rs and Rn are expressions evaluating to a register number other than R15.
4.6.5 Examples
MUL
MLAEQS
R1,R2,R3
R1,R2,R3,R4
; R1:=R2*R3
; conditionally R1:=R2*R3+R4,
; setting condition codes
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