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參數(shù)資料
| 型號： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數(shù)： | 81/120頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
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Instruction Cycle Operations
77
7.3 Multiply and multiply accumulate
The multiply instructions make use of special hardware which implements a 2 bit Booth's algorithm with
early termination. During the first cycle the accumulate Register is brought to the ALU, which either
transmits it or produces zero (depending on the instruction being MLA or MUL) to initialise the destination
register. During the same cycle, the multiplier (Rs) is loaded into the Booth's shifter via the A bus.
The datapath then cycles, adding the multiplicand (Rm) to, subtracting it from, or just transmitting, the
result register. The multiplicand is shifted in the Nth cycle by 2N or 2N+1 bits, under control of the Booth's
logic. The multiplier is shifted right 2 bits per cycle, and when it is zero the instruction terminates (possibly
after an additional cycle to clear a pending borrow).
All cycles except the first are internal. The cycle timings are shown below in
Table 9: Multiply Instruction
Cycle Operations
.
m
is the number of cycles required by the Booth's algorithm; see the section on instruction speeds.
Cycle
Address
nBW
nRW
Data
nMREQ
SEQ
nOPC
(Rs)=0,1
1
pc+8
1
0
(pc+8)
1
0
0
2
pc+12
1
0
-
0
1
1
pc+12
(pc+8)
(Rs)>1
1
pc+8
1
0
(pc+8)
1
0
0
2
pc+12
1
0
-
1
0
1
pc+12
1
0
-
1
0
1
m
pc+12
1
0
-
1
0
1
m+1
pc+12
1
0
-
0
1
1
pc+12
Table 9: Multiply Instruction Cycle Operations
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