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March 2001
Copyright Alliance Semiconductor. All rights reserved.
AS29LV800
3V 1M × 8/512K × 16 CMOS Flash EEPROM
3/22/01;
V.1.0
Alliance Semiconductor
P. 1 of 25
Features
Organization: 1M×8/512K×16
Sector architecture
- One 16K; two 8K; one 32K; and fifteen 64K byte sectors
- One 8K; two 4K; one 16K; and fifteen 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
Single 2.7-3.6V power supply for read/write operations
Sector protection
High speed 70/80/90/120 ns address access time
Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
Hardware RESET pin
- Resets internal state machine to read mode
Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- DQ2 toggle bit
- RY/BY output
Erase suspend/resume
- Supports reading data from or programming data to a
sector not being erased
Low V
CC
write lock-out below 1.5V
10 year data retention at 150C
100,000 write/erase cycle endurance
Logic block diagram
X decoder
V
CC
V
SS
Cell matrix
Y decoder
Y gating
Data latch
Chip enable
Output enable
Logic
A
Input/output
buffers
Serase voltage
Command
register
Program/erase
control
V
CC
detector
Erase voltage
generator
Program voltage
generator
Timer
A0–A18
CE
OE
A-1
STB
STB
RY/
BY
WE
RESET
DQ0–DQ15
switches
BYTE
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44-pin SO
A10
A11
A12
A13
2
3
4
A18
A17
A7
1
RY/BY
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
WE
A8
A9
RESET
A
A
A
A
A
A
A
A
A
B
V
S
D
D
D
N
N
W
R
N
N
R
A
D
D
D
D
V
C
D
D
D
D
D
1
2
3
4
5
6
7
8
9
1
1
1
1
1
4
4
4
4
4
4
4
4
4
3
3
3
3
3
1
1
3
3
48-pin TSOP
A
A
A
A
A
A
A
A
A
C
V
S
O
D
D
D
D
1
1
1
2
2
2
3
3
3
2
2
2
2
2
2
2
AS29LV800
A
Selection guide
29LV800-70R
*
* Regulated voltage range of 3.0 to 3.6V
29LV800-80
29LV800-90
29LV800-120
Unit
Maximum access time
t
AA
t
CE
t
OE
70
80
90
120
ns
Maximum chip enable access time
70
80
90
120
ns
Maximum output enable access time
30
30
35
50
ns