參數(shù)資料
型號(hào): AS29LV800T-80RTC
元件分類: EEPROM
英文描述: EEPROM
中文描述: EEPROM的
文件頁數(shù): 7/25頁
文件大?。?/td> 463K
代理商: AS29LV800T-80RTC
AS29LV800
3/22/01;
V.1.0
Alliance Semiconductor
P. 7 of 25
March 2001
Command definitions
Item
Description
Reset/Read
Initiate read or reset operations by writing the Read/Reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read
mode until command register contents are altered.
Device automatically powers up in read/reset state. This feature allows only reads, therefore
ensuring no spurious memory content alterations during power up.
ID Read
AS29LV800 provides manufacturer and device codes in two ways. External PROM programmers
typically access the device codes by driving +10V on A9. AS29LV800 also contains an ID Read
command to read the device code with only +3V since multiplexing +10V on address lines is
generally undesirable.
Initiate device ID read by writing the ID Read command sequence into the command register.
Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command
sequence with a read sequence from address XXX01h to return device code.
To verify write protect status on sectors, read address XXX02h. Sector addresses A18–A12 produce
a 1 on DQ0 for protected sector and a 0 for unprotected sector.
Exit from ID read mode with Read/Reset command sequence.
Hardware Reset
Holding RESET low for 500 ns resets the device, terminating any operation in progress; data
handled in the operation is corrupted. The internal state machine resets 20 μs after RESET is driven
low. RY/BY remains low until internal state machine resets. After RESET is set high, there is a delay
of 50 ns for the device to permit read operations.
Byte/word
Programming
Programming the AS29LV800 is a four bus cycle operation performed on a byte-by-byte or word-
by-word basis. Two unlock write cycles precede the Program Setup command and program data
write cycle. Upon execution of the program command, no additional CPU controls or timings are
necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched
on the rising edge of CE or WE, whichever is first. The AS29LV800’s automated on-chip program
algorithm provides adequate internally-generated programming pulses and verifies the
programmed cell margin.
Check programming status by sampling data on the RY/BY pin, or either the DATA polling (DQ7)
or toggle bit (DQ6) at the program address location. The programming operation is complete if
DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/BY pin = high.
The AS29LV800 ignores commands written during programming. A hardware reset occurring
during programming may corrupt the data at the programmed location.
AS29LV800 allows programming in any sequence, across any sector boundary. Changing data from
0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1
(exceeded programming time limits); reading this data after a read/reset operation returns a 0.
When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this
state, a Reset command returns the device to read mode.
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