參數(shù)資料
型號: AS5C4008DJECJ-17
英文描述: x8 SRAM
中文描述: x8的SRAM
文件頁數(shù): 5/12頁
文件大?。?/td> 136K
代理商: AS5C4008DJECJ-17
S R A M
AS5C4009
Austin Semiconductor, Inc.
AS5C4009
Rev. 5.0 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 3ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load ......................................... See Figures 1
NOTES
1.
Overshoot: Vcc +3.0V for pulse width < 20ms.
2.
Undershoot: -3V for pulse width < 20ms.
3.
I
is dependent on output loading and cycle rates.
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
At any given temperature and voltage condition,
t
HZCE
is less than
t
LZCE
, and
t
HZWE
is less than
t
LZWE
.
7.
WE\ is HIGH for READ cycle.
8.
Device is continuously selected. Chip enables and
output enables are held in their active state.
9.
Address valid prior to, or coincident with, latest
occurring chip enable.
10.
11. Chip enable and write enable can initiate and
terminate a WRITE cycle.
12. Output enable (OE\) is inactive (HIGH).
13. Output enable (OE\) is active (LOW).
14. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
15. All voltage referenced to Vss (GND).
t
RC = Read Cycle Time.
Fig. 1 Output Load Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
V
CC
for Retention Data
SYMBOL
V
DR
I
CCDR
MIN
2
MAX
UNITS
V
NOTES
CE\ > (V
CC
- 0.2V)
V
CC
= 2V
100
μ
A
V
IN
> (V
CC
- 0.2V)
V
CC
= 3V
I
CCDR
200
μ
A
Chip Deselect to Data
Retention Time
t
CDR
0
ns
4
Operation Recovery Time
t
R
5
ms
4, 10
Data Retention Current
CONDITIONS
50 ohms
1.73V
C = 100pF
Q
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