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參數(shù)資料
| 型號(hào)： | AS5C4009LL |
| 英文描述： | 512K x 8 SRAM |
| 中文描述： | 為512k × 8的SRAM |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 136K |
| 代理商： | AS5C4009LL |
S R A M
AS5C4009
Austin Semiconductor, Inc.
AS5C4009
Rev. 5.0 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55
o
C < T
A
< 125
o
C; Vcc = 5V +10%)
CAPACITANCE
PARAMETER
SYMBOL
MAXIMUM
UNITS
NOTES
Input Capacitance
V
IN
=0V
C
IN
8
pF
4
Input/Output Capactiance
V
IO
=0V
C
IO
10
pF
4
T
A
= 25
o
C, f = 1MHz
V
CC
= 5V
CONDITIONS
SYM
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
READ Cycle
READ cycle Time
t
t
t
t
t
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
RC
55
70
85
100
ns
Address access time
AA
55
70
85
100
ns
Chip Enable access time
ACE
55
70
85
100
ns
Output hold from address change
OH
10
10
10
10
ns
Chip Enable to output in Low-Z
LZCE
10
10
10
10
ns
4,6
Chip disable to output in High-Z
20
25
30
30
ns
4,6
Chip Enable to power-up time
0
0
0
0
ns
4
Chip disable to power-down time
55
70
85
100
ns
4
Output Enable access time
30
35
40
45
ns
Output Enable to output in Low-Z
5
5
5
5
ns
4,6
Output disable to output in High-Z
WRITE Cycle
20
25
30
30
ns
4,6
WRITE cycle time
t
t
t
t
t
t
t
t
t
LZWE
t
HZWE
WC
55
70
85
100
ns
Chip Enable to end of write
CW
50
60
70
80
ns
Address valid to end of write
AW
50
60
70
80
ns
Address setup time
AS
0
0
0
0
ns
Address hold from end of write
AH
0
0
0
0
ns
WRITE pulse width
WP1
50
60
70
80
ns
Data setup time
DS
30
30
35
40
ns
Data hold time
DH
0
0
0
0
ns
Write disable to output in Low-Z
5
5
5
5
ns
4,6
Write Enable to output in High-Z
25
25
30
30
ns
4,6
-100
DESCRIPTION
-55
-70
-85
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|---|---|
| AS5C4009LL-100CW/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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| AS5C4009LL-55CW/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| AS5C4009LL-55ECJ/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| AS5C4009LL-70CW/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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