參數(shù)資料
型號(hào)： AS5SS256K36ADQ-8.5/883C
廠商： AUSTIN SEMICONDUCTOR INC
元件分類： SRAM
英文描述： 256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM
中文描述： 256K X 36 STANDARD SRAM, 8.5 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, MS-026, TQFP-100
文件頁(yè)數(shù)： 5/16頁(yè)
文件大小： 391K
代理商： AS5SS256K36ADQ-8.5/883C
SSRAM
AS5SS256K36 &
AS5SS256K36A
AS5SS256K36 &
AS5SS256K36A
Rev. 3.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
Austin Semiconductor, Inc.
NOTE:
1. D(A2) refers to output from address A2. D(A2+1) refers to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable
inputs being sampled.
4. ADV\ must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BEW\, BWa\ - BWd\ LOW.
WRITE TIMING PARAMETERS
MIN
MAX
MIN
MAX
tKC
10.0
15
ns
tKF
100
66
MHz
tKH
3.0
4.0
ns
tKL
3.0
4.0
ns
tOEHZ
5.0
ns
tAS
1.8
2.0
ns
tADSS
1.8
2.0
ns
tAAS
1.8
2.0
ns
tWS
1.8
2.0
ns
SYMBOL
-8.5
-10
UNITS
MIN
MAX
MIN
MAX
tDS
1.8
2.0
ns
tCES
1.8
2.0
ns
tAH
0.5
ns
tADSH
0.5
ns
tAAH
0.5
ns
tWH
0.5
ns
tDH
0.5
ns
tCEH
0.5
ns
SYMBOL
-8.5
-10
UNITS
WRITE TIMING
12345
123456789
12345
123456
12345
1234
123456789
12345
1234
12345
1234
123456789
1234
12345
123456789012
1234567
12
1234
123456789
1234
12345
1234
123456789
12345
1234
12345
123456789
12345
1234
1234567890
12345
1234
123456789
12345
1234
12345
123456789
1234
12345
CLK
ADSP\
ADSS
ADSC\
○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○
○○○○○○○
○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○○○
○
○○○○○○○○○○○○○○○○○○
○
○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○
○○○○
○
○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○
○
○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○
○○○○○○○○○○
○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○
○○○○○○○○○
○
○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○
○○○○○○○
ADDRESS
BWE\
BWa\ - BWd\
○
○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○
CE\
(See Note)
ADV\
OE\
t
ADSH
t
AS
t
AH
tDS
Single WRITE
BURST WRITE
GW\
○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○○○○○○○○○○○
D
Extended BURST WRITE
t
12345
12345678
123
12345678
123456789012345678901234567890121234567890123
12
1
A3
123456789
123456789012345678901
12
123456789012345678
1234567890123
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901
12
1234
123456789
12
D(A2)
D(A2+1)
D(A2+2)
12
D(A2+3)
12
D(A3)
12
D(A3+1)
12
D(A3+2)
123456
1234567
123456
12345
123456
12345
12345678
12
12345
12345678901234567
123456
12345
123456
12345
1234567890123456789012345678901212345678901234567890
1234
12345
1234
123456
1234567890123456789012345
12
12345
123456
12345
D(A1)
D(A2+1)
t
KC
t
KL
t
KH
1234567890
Q
High-Z
12
ADSS
t
ADSH
t
A1
A2
BYTE WRITE signals are
ignored when ADSP\ is LOW.
ADSS
t
ADSH
t
BURST READ
ADSC\ extends burst.
123456
WS
tWH
t
WS
tWH
t
(Note 5)
CES
t
CEH
t
(Note 4)
AAS
t
AAH
t
ADV\ suspends burst.
(Note 3)
tDH
tOEHZ
(Note 1)
12345
1234
Don’t Care
Undefined
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