參數(shù)資料
型號: AS8510-ASST
廠商: ams
文件頁數(shù): 26/47頁
文件大?。?/td> 0K
描述: IC BATTERY MANAGEMENT 20-SSOP
產(chǎn)品培訓(xùn)模塊: AS8510 Data Acquisition IC
標(biāo)準(zhǔn)包裝: 2,000
類型: 電池管理
輸入類型: 模擬,數(shù)字
輸出類型: 模擬,數(shù)字
接口: SPI 串行
電流 - 電源: 5mA
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 帶卷 (TR)
Revision 3.5
31 - 46
AS8510
Datasheet - Detailed Descr i p ti on
Digital Control Registers
08
CLK_REG
(Clock Control Register)
0010_0000
R/W
D[7:6]
Oversampling frequency clock selection. Default is 00
(high speed (HS) internal Clock)
00
Internal HS Clock with No Clock Output
01
Internal HS Clock with Clock Output
10
External Clock
D[5:4]
These two bits select the division ratio for HS clock/
external clock. Default is 10 (division by 4)
00
No division
01
Divide by 2
10
Divide by 4
11
Divide by 8
D[3:2]
These two bits select the division ratio of HS clock, by
which it should be divided before providing it on CLK
pin. Default is 00 (No Division)
00
No Division
01
Divide by 2
10
Divide by 4
11
Divide by 8
D[1]
This bit selects the division ratio of LS clock
0
LS _CLK undivided (Low Speed clock)
1
LS _CLK divide by 2
D[0]
Reserved
09
RESET_REG
(Reset Control Register)
1100_0000
R/W
D[7]
Entire device can be soft reset by writing “0” into this
register bit. This bit will take a default 1 value on coming
out of Reset
D[6]
Measurement Path can be soft reset by writing “0” into
this register bit. This bit will take a default 1 value after
Measurement Path is reset.
D[5:0]
Reserved
Table 33. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
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