參數(shù)資料
型號(hào): AT17LV512A-10PI
廠(chǎng)商: Atmel
文件頁(yè)數(shù): 3/18頁(yè)
文件大?。?/td> 0K
描述: IC CONFIG SEEPROM 512K 8DIP
標(biāo)準(zhǔn)包裝: 50
可編程類(lèi)型: 串行 EEPROM
存儲(chǔ)容量: 512kb
電源電壓: 3 V ~ 3.6 V,4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-DIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 609 (CN2011-ZH PDF)
配用: ATDH2225-ND - CABLE ISP FOR AT17
ATDH2200E-ND - CONFIGURATOR PROGRAM BOARD KIT
11
2322G–CNFG–03/06
AT17LV65A/128A/256A/512A/002A
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Notes:
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
19. AC Characteristics
V
CC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
Symbol
Description
AT17LV65A/128A/256A
AT17LV512A/010A/002A
Units
Commercial
Industrial
Commercial
Industrial
Min
Max
Min
Max
Min
Max
Min
Max
T
OE to Data Delay
30
35
30
35
ns
T
CE
CE to Data Delay
45
ns
T
CAC
CLK to Data Delay
50
55
50
ns
T
OH
Data Hold from CE, OE, or CLK
0
ns
T
DF
CE or OE to Data Float Delay
50
ns
T
LC
CLK Low Time
20
ns
T
HC
CLK High Time
20
ns
T
SCE
CE Setup Time to CLK (to guarantee proper
counting)
35
40
20
25
ns
T
HCE
CE Hold Time from CLK (to guarantee proper
counting)
000
0
ns
T
HOE
OE High Time (guarantees counter is reset)
20
ns
F
MAX
Maximum Input Clock Frequency
12.5
15
MHz
20. AC Characteristics when Cascading
V
CC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial
Symbol
Description
AT17LV65A/128A/256A
AT17LV512A/010A/002A
Units
Commercial
Industrial
Commercial
Industrial
Min
Max
Min
Max
Min
Max
Min
Max
T
CDF
CLK to Data Float Delay
50
ns
T
OCK
CLK to CEO Delay
3540
ns
T
OCE
CE to CEO Delay
3535
ns
T
OOE
RESET/OE to CEO Delay
3035
3030
ns
F
MAX
Maximum Input Clock Frequency
10
12.5
MHz
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