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參數(shù)資料
| 型號： | AT17LV65A-10BJC |
| 廠商： | Atmel Corp. |
| 元件分類： | FPGA |
| 英文描述： | FPGA Configuration EEPROM Memory |
| 中文描述： | FPGA配置EEPROM存儲器 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | AT17LV65A-10BJC |
8
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17LV
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as
well as Xilinx applications.
Control of
Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are sim-
ple and self-explanatory.
The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17LV series
configurator.
The CEO output of any AT17LV series configurator drives the CE input of the next
configurator in a cascaded chain of EEPROMs.
SER_EN must be connected to VCC (except during ISP).
The READY
(1) pin is available as an open-collector indicator of the device’s reset
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.
Note:
1. This pin is not available for the AT17LV65/128/256 devices.
Cascading Serial
Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configu-
ration memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator
asserts its CEO output Low and disables its DATA line driver. The second configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are
reset if the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
AT17LV Series Reset
Polarity
The AT17LV series configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the Two-Wire serial bus. The programming is done at V
CC supply
only. Programming super voltages are generated inside the chip.
Standby Mode
The AT17LV series configurators enter a low-power standby mode whenever CE is
asserted High. In this mode, the AT17LV65/128/256 configurator consumes less than
50 A of current at 3.3V (100 A for the AT17LV512/010 and 200 A for the
AT17LV002/040). The output remains in a high-impedance state regardless of the state
of the OE input.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV65A-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV65A-10JC | 功能描述:FPGA-配置存儲器 ASICS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| AT17LV65A-10JI | 功能描述:FPGA-配置存儲器 ASICS RoHS:否 制造商:Altera Corporation 存儲類型:Flash 存儲容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
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