參數(shù)資料
型號(hào)： AT17LV65A-10SC
廠商： Atmel Corp.
英文描述： High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SO -55 to 125
中文描述： FPGA配置EEPROM存儲(chǔ)器
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 221K
代理商： AT17LV65A-10SC
5
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
Block Diagram
Notes:
1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17LV series configurator. If CE is held High after
the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-
stated. When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
POWER ON
RESET
SER_EN
WP1
(2)
WP2
(2)
(1)
READY
(2)
相關(guān)PDF資料
PDF描述
AT17LV65A-10SI High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SO -55 to 125
AT17LV65A-10TQC High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-TSSOP -55 to 125
AT17LV65A-10TQI High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-TSSOP -55 to 125
AT32UC3B1128 32-Bit Microcontroller
AT32UC3B1256 32-Bit Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT17LV65A-10SI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
AT17LV65A-10TQC 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
AT17LV65A-10TQI 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory
AT17LVXXXA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA Configuration EEPROM 65K. 128K and 256K
AT17N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AT17N/256/512/010/002/040 [Updated 5/03. 18 Pages]
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