參數(shù)資料
型號(hào): AT30TS750-XM8-B
廠商: ATMEL CORP
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 3Cel, SQUARE, SURFACE MOUNT
封裝: 3 X 3 MM, GREEN, PLASTIC, MSOP-8
文件頁(yè)數(shù): 49/52頁(yè)
文件大小: 1369K
代理商: AT30TS750-XM8-B
R
3.
Block Diagram
Figure 3-1.
Block Diagram
SCL
SDA
ALERT
TEMPERATURE
SENSOR
ΣΔ
A/D
CONVERTER
POINTER
REGISTER
I2C/SMBus
INTERFACE
CONTROL
AND
LOGIC
A2-0
TEMPERATURE
REGISTER
DIGITAL
COMPARATOR
3
CONFIGURATION
REGISTER
NONVOLATILE
CONFIGURATION
REGISTER
THIGH LIMIT
REGISTER
NONVOLATILE
THIGH LIMIT
REGISTER
TLOW LIMIT
REGISTER
NONVOLATILE
TLOW LIMIT
REGISTER
4.
Device Communication
The AT30TS750 operates as a slave device and utilizes a simple 2-wire I2C and SMBus
compatible digital serial interface to communicate with a host controller, commonly referred to as
the bus Master.
The Master initiates and controls all read and write operations to the slave
devices on the serial bus, and both the Master and the slave devices can transmit and receive
data on the bus.
The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data
(SDA). The SCL pin is used to receive the clock signal from the Master, while the bidirectional
SDA pin is used to receive command and data information from the Master as well as to send
data back to the Master. Data is always latched into the AT30TS750 on the rising edge of SCL
and always output from the device on the falling edge of SCL.
Both the SCL and SDA pin
incorporate integrated spike suppression filters and Schmitt triggers to minimize the effects of
input spikes and bus noise.
All command and data information is transferred with the most-significant bit (MSB) first. During
bus communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of
data has been transferred, the receiving device must respond with either an acknowledge (ACK)
or a no-acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle)
generated by the Master. Therefore, nine clock cycles are required for every one byte of data
transferred. There are no unused clock cycles during any read or write operation, so there must
not be any interruptions or breaks in the data stream during each data byte transfer and ACK or
NACK clock cycle.
8749A-DTS-03/11
Atmel AT30TS750 [Preliminary]
6
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