參數(shù)資料
型號: AT30TS750-XM8-T
廠商: ATMEL CORP
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 3Cel, SQUARE, SURFACE MOUNT
封裝: 3 X 3 MM, GREEN, PLASTIC, MSOP-8
文件頁數(shù): 19/52頁
文件大小: 1369K
代理商: AT30TS750-XM8-T
R
Table 6-10.
Fault Tolerance Queue
NVFT1
NVFT0
Consecutive Faults Required
0
1
0
1
2
1
0
4
1
6
6.4.3
NVPOL Bit
The nonvolatile NVPOL bit controls the power-up/reset default ALERT pin polarity. When the
NVPOL bit is set to the logic “0” state, the ALERT pin will be an active low output after the device
powers up or resets. Conversely, when the NVPOL bit is set to the logic “1” state, the ALERT pin
will be an active high output. The NVPOL bit is set from the factory to default to the logic “0” state.
6.4.4
NVCMP/INT Bit
The nonvolatile NVCMP/INT bit controls whether the device will operate in the Comparator Mode
or the Interrupt Mode after a power-up or reset sequence. Setting the NVCMP/INT bit to the logic
“0” state (the factory default setting) will allow the device to power-up/reset in the Comparator
Mode. Alternatively, when the NVCMP/INT bit is set to the logic “1” state, the device will power-
up/reset in the Interrupt Mode.
6.4.5
NVSD Bit
The nonvolatile NVSD bit is used to enable the device to power-up/reset in the Shutdown Mode.
When the NVSD bit is in the logic “0” state, the device will power-up/reset in the normal
operational mode and perform continuous temperature measurements and conversions. When
the NVSD bit is set to the logic “1” state, the device will automatically enter the Shutdown Mode
after a power-up or reset sequence (see the Shutdown Mode section on page 13 for more details).
The NVSD bit is factory-set to the logic “0” state.
6.4.6
RLCKDWN
The one-time programmable RLCKDWN bit controls whether or not both the volatile and
nonvolatile versions of the configuration and limit registers will be permanently locked down.
Once the RLCKDWN bit is set to the logic “1” state, the Configuration Register, TLOW Limit
Register, THIGH Limit Register, Nonvolatile Configuration Register, Nonvolatile TLOW Limit
Register, and Nonvolatile THIGH Limit Register will be locked down and can never be modified
again. Since the RLCKDWN bit is one-time programmable, once the bit is set to the logic “1”
state, it cannot be reset again. The RLCKDWN bit takes priority over the RLCK bit (see the
Register Locking section on page 33 for more details) and is factory-set to the logic “0” state.
6.4.7
RLCK
The nonvolatile RLCK bit controls the reversible locking of both the volatile and nonvolatile
configuration and limit registers. When the RLCK bit is set to the logic “0” state, the Configuration
Register, TLOW Limit Register, THIGH Limit Register, Nonvolatile Configuration Register,
Nonvolatile TLOW Limit Register, and Nonvolatile THIGH Limit Register will be unlocked and can
be modified.
Alternatively, when the RLCK bit is set to the logic “1” state, the volatile and
nonvolatile configuration and limit registers will be locked and cannot be modified. When the
8749A-DTS-03/11
Atmel AT30TS750 [Preliminary]
26
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PDF描述
AT30TS750-MA8-T DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 3Cel, RECTANGULAR, SURFACE MOUNT
AT30TS750-XM8-B DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 3Cel, SQUARE, SURFACE MOUNT
AT42QT1070-SSU PROXIMITY SENSOR-CAPACITIVE, 0.6-2.6V, RECTANGULAR, SURFACE MOUNT
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