參數(shù)資料
型號: AT30TS750-XM8-T
廠商: ATMEL CORP
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 3Cel, SQUARE, SURFACE MOUNT
封裝: 3 X 3 MM, GREEN, PLASTIC, MSOP-8
文件頁數(shù): 50/52頁
文件大?。?/td> 1369K
代理商: AT30TS750-XM8-T
Atmel AT30TS750 [Preliminary]
During data transfers, data on the SDA pin must only change while SCL is low, and the data must
remain stable while SCL is high. If data on the SDA pin changes while SCL is high, then either a
START or a STOP condition will occur. START and STOP conditions are used to initiate and end
all serial bus communication between the Master and the slave devices. The number of data
bytes transferred between a START and a STOP condition is not limited and is determined by the
Master.
In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic-high state at
the same time.
4.1
START Condition
A START condition occurs when there is a high-to-low transition on the SDA pin while the SCL
pin is stable in the logic-high state. The Master uses a START condition to initiate any data
transfer sequence, and the START condition must precede any command. The AT30TS750 will
continuously monitor the SDA and SCL pins for a START condition, and the device will not
respond unless one is given.
4.2
STOP Condition
A STOP condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin
is stable in the logic-high state. The Master uses the STOP condition to end a data transfer
sequence to the AT30TS750, which will subsequently return to the idle state. The Master can
also utilize a repeated START condition instead of a STOP condition to end the current data
transfer if the Master will perform another operation.
4.3
Acknowledge (ACK)
After every byte of data received, the AT30TS750 must acknowledge to the Master that it has
successfully received the data byte by responding with an ACK. This is accomplished by the
Master first releasing the SDA line and providing the ACK/NACK clock cycle (a ninth clock cycle
for every byte). During the ACK/NACK clock cycle, the AT30TS750 must output a logic “0” (ACK)
for the entire clock cycle such that the SDA line must be stable in the logic-low state during the
entire high period of the clock cycle.
4.4
No-Acknowledge (NACK)
When the AT30TS750 is transmitting data to the Master, the Master can indicate that it is done
receiving data and wants to end the operation by sending a NACK response to the AT30TS750
instead of an ACK response. This is accomplished by the Master outputting a logic “1” during the
ACK/NACK clock cycle, at which point the AT30TS750 will release the SDA line so that the
Master can then generate a STOP condition.
In addition, the AT30TS750 can use a NACK to respond to the Master instead of an ACK for
certain invalid operation cases such as an attempt to write to a read-only register (e.g. an attempt
to write to the Temperature Register).
8749A-DTS-03/11
7
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相關(guān)PDF資料
PDF描述
AT30TS750-MA8-T DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 3Cel, RECTANGULAR, SURFACE MOUNT
AT30TS750-XM8-B DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 3Cel, SQUARE, SURFACE MOUNT
AT42QT1070-SSU PROXIMITY SENSOR-CAPACITIVE, 0.6-2.6V, RECTANGULAR, SURFACE MOUNT
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