60
AT32UC3A
Notes:
1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF.
2. tCPMCK: Master Clock period in ns.
12.12 MACB Characteristics
Notes:
1. f: MCK frequency (MHz)
2. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF
Table 12-30. SPI Timings
Symbol
Parameter
Conditions
Min
Max
Units
SPI
0
MISO Setup time before SPCK rises (master)
22 + (t
CPMCK)/2
ns
SPI
1
MISO Hold time after SPCK rises (master)
0ns
SPI
2
SPCK rising to MOSI Delay (master)
7ns
SPI
3
MISO Setup time before SPCK falls (master)
22 + (t
CPMCK)/2
ns
SPI
4
MISO Hold time after SPCK falls (master)
0ns
SPI
5
SPCK falling to MOSI Delay (master)
7ns
SPI
6
SPCK falling to MISO Delay (slave)
26.5
ns
SPI
7
MOSI Setup time before SPCK rises (slave)
0ns
SPI
8
MOSI Hold time after SPCK rises (slave)
1.5
ns
SPI
9
SPCK rising to MISO Delay (slave)
27
ns
SPI
10
MOSI Setup time before SPCK falls (slave)
0ns
SPI
11
MOSI Hold time after SPCK falls (slave)
1ns
Table 12-31. Ethernet MAC Signals
Symbol
Parameter
Conditions
Min (ns)
Max (ns)
EMAC
1
Setup for EMDIO from EMDC rising
EMAC2
Hold for EMDIO from EMDC rising
EMAC
3
EMDIO toggling from EMDC falling
Table 12-32. Ethernet MAC MII Specific Signals
Symbol
Parameter
Conditions
Min (ns)
Max (ns)
EMAC
4
Setup for ECOL from ETXCK rising
3
EMAC
5
Hold for ECOL from ETXCK rising
0
EMAC6
Setup for ECRS from ETXCK rising
3
EMAC
7
Hold for ECRS from ETXCK rising
0
EMAC8
ETXER toggling from ETXCK rising
15
EMAC9
ETXEN toggling from ETXCK rising
15
EMAC
10
ETX toggling from ETXCK rising
15
EMAC11
Setup for ERX from ERXCK
1
32058KS–AVR32–01/12