1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor" />
參數(shù)資料
型號: AT32UC3A0128-ALUT
廠商: Atmel
文件頁數(shù): 57/97頁
文件大?。?/td> 0K
描述: IC MCU AVR32 128KB FLASH 144LQFP
產(chǎn)品培訓模塊: AVR UC3 Audio Application
MCU Product Line Introduction
AVR EVK1105 Digital Audio Gateway Kit
AVR® UC3 Introduction
標準包裝: 300
系列: AVR®32 UC3 A0
核心處理器: AVR
芯體尺寸: 32-位
速度: 66MHz
連通性: EBI/EMI,以太網(wǎng),I²C,SPI,SSC,UART/USART,USB OTG
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 109
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
配用: ATSTK600-RC33-ND - STK600 ROUTING CARD AVR
ATEVK1105-ND - KIT EVAL FOR AT32UC3A0
ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATEVK1100-ND - KIT DEV/EVAL FOR AVR32 AT32UC3A
60
AT32UC3A
Notes:
1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF.
2. tCPMCK: Master Clock period in ns.
12.12 MACB Characteristics
Notes:
1. f: MCK frequency (MHz)
2. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF
Table 12-30. SPI Timings
Symbol
Parameter
Conditions
Min
Max
Units
SPI
0
MISO Setup time before SPCK rises (master)
3.3V domain(1)
22 + (t
CPMCK)/2
ns
SPI
1
MISO Hold time after SPCK rises (master)
3.3V domain(1)
0ns
SPI
2
SPCK rising to MOSI Delay (master)
3.3V domain(1)
7ns
SPI
3
MISO Setup time before SPCK falls (master)
3.3V domain(1)
22 + (t
CPMCK)/2
ns
SPI
4
MISO Hold time after SPCK falls (master)
3.3V domain (1)
0ns
SPI
5
SPCK falling to MOSI Delay (master)
3.3V domain (1)
7ns
SPI
6
SPCK falling to MISO Delay (slave)
3.3V domain (1)
26.5
ns
SPI
7
MOSI Setup time before SPCK rises (slave)
3.3V domain (1)
0ns
SPI
8
MOSI Hold time after SPCK rises (slave)
3.3V domain (1)
1.5
ns
SPI
9
SPCK rising to MISO Delay (slave)
3.3V domain (1)
27
ns
SPI
10
MOSI Setup time before SPCK falls (slave)
3.3V domain (1)
0ns
SPI
11
MOSI Hold time after SPCK falls (slave)
3.3V domain (1)
1ns
Table 12-31. Ethernet MAC Signals
Symbol
Parameter
Conditions
Min (ns)
Max (ns)
EMAC
1
Setup for EMDIO from EMDC rising
Load: 20pF(2)
EMAC2
Hold for EMDIO from EMDC rising
Load: 20pF(2)
EMAC
3
EMDIO toggling from EMDC falling
Load: 20pF(2)
Table 12-32. Ethernet MAC MII Specific Signals
Symbol
Parameter
Conditions
Min (ns)
Max (ns)
EMAC
4
Setup for ECOL from ETXCK rising
Load: 20pF (1)
3
EMAC
5
Hold for ECOL from ETXCK rising
Load: 20pF (1)
0
EMAC6
Setup for ECRS from ETXCK rising
Load: 20pF (1)
3
EMAC
7
Hold for ECRS from ETXCK rising
Load: 20pF (1)
0
EMAC8
ETXER toggling from ETXCK rising
Load: 20pF (1)
15
EMAC9
ETXEN toggling from ETXCK rising
Load: 20pF (1)
15
EMAC
10
ETX toggling from ETXCK rising
Load: 20pF (1)
15
EMAC11
Setup for ERX from ERXCK
Load: 20pF (1)
1
32058KS–AVR32–01/12
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