TABLE 23-35: I2
參數(shù)資料
型號: AT32UC3L032-D3HR
廠商: Atmel
文件頁數(shù): 43/174頁
文件大小: 0K
描述: MCU AVR32 32K FLASH 48TTLGA
產(chǎn)品培訓模塊: AVR® UC3 Introduction
標準包裝: 1
系列: AVR®32 UC3 L
核心處理器: AVR
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-UFLGA
包裝: 標準包裝
其它名稱: AT32UC3L032-D3HRDKR
dsPIC30F6011/6012/6013/6014
DS70117F-page 202
2006 Microchip Technology Inc.
TABLE 23-35: I2C BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature
-40°C
≤ TA ≤ +85°C for Industrial
-40°C
≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min(1)
Max
Units
Conditions
IM10
TLO:SCL
Clock Low Time 100 kHz mode
TCY/2 (BRG + 1)
μs—
400 kHz mode
TCY/2 (BRG + 1)
μs—
1 MHz mode(2)
TCY/2 (BRG + 1)
μs—
IM11
THI:SCL
Clock High Time 100 kHz mode
TCY/2 (BRG + 1)
μs—
400 kHz mode
TCY/2 (BRG + 1)
μs—
1 MHz mode(2)
TCY/2 (BRG + 1)
μs—
IM20
TF:SCL
SDA and SCL
Fall Time
100 kHz mode
300
ns
CB is specified to be
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
100
ns
IM21
TR:SCL
SDA and SCL
Rise Time
100 kHz mode
1000
ns
CB is specified to be
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
300
ns
IM25
TSU:DAT
Data Input
Setup Time
100 kHz mode
250
ns
400 kHz mode
100
ns
1 MHz mode(2)
TBD
ns
IM26
THD:DAT Data Input
Hold Time
100 kHz mode
0
ns
400 kHz mode
0
0.9
μs
1 MHz mode(2)
TBD
ns
IM30
TSU:STA
Start Condition
Setup Time
100 kHz mode
TCY/2 (BRG + 1)
μs
Only relevant for
repeated Start
condition
400 kHz mode
TCY/2 (BRG + 1)
μs
1 MHz mode(2)
TCY/2 (BRG + 1)
μs
IM31
THD:STA Start Condition
Hold Time
100 kHz mode
TCY/2 (BRG + 1)
μs
After this period the
first clock pulse is
generated
400 kHz mode
TCY/2 (BRG + 1)
μs
1 MHz mode(2)
TCY/2 (BRG + 1)
μs
IM33
TSU:STO Stop Condition
Setup Time
100 kHz mode
TCY/2 (BRG + 1)
μs—
400 kHz mode
TCY/2 (BRG + 1)
μs
1 MHz mode(2)
TCY/2 (BRG + 1)
μs
IM34
THD:STO Stop Condition
100 kHz mode
TCY/2 (BRG + 1)
ns
Hold Time
400 kHz mode
TCY/2 (BRG + 1)
ns
1 MHz mode(2)
TCY/2 (BRG + 1)
ns
IM40
TAA:SCL
Output Valid
From Clock
100 kHz mode
3500
ns
400 kHz mode
1000
ns
1 MHz mode(2)
——
ns
IM45
TBF:SDA Bus Free Time
100 kHz mode
4.7
μs
Time the bus must be
free before a new
transmission can start
400 kHz mode
1.3
μs
1 MHz mode(2)
TBD
μs
IM50
CB
Bus Capacitive Loading
400
pF
Note 1:
BRG is the value of the I2C Baud Rate Generator. Refer to the “Inter-Integrated Circuit (I2C)” section
in the “dsPIC30F Family Reference Manual” (DS70046).
2:
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
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