參數(shù)資料
型號(hào)： AT32UC3L032-D3UR
廠商： Atmel
文件頁數(shù)： 89/174頁
文件大小： 0K
描述： MCU AVR32 32KB FLASH 48TLLGA
標(biāo)準(zhǔn)包裝： 8,000
系列： AVR®32 UC3 L
核心處理器： AVR
芯體尺寸： 32-位
速度： 50MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-UFLGA
包裝： 帶卷 (TR)
其它名稱： 32UC3L032-D3UR
32UC3L032-D3UR-ND
40
32099I–01/2012
AT32UC3L016/32/64
6.1.4
Power-up Sequence
6.1.4.1
Maximum Rise Rate
To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values
Recommended order for power supplies is also described in this chapter.
6.1.4.2
Minimum Rise Rate
The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply
requires a minimum rise rate for the VDDIN power supply.
See Table 32-3 on page 771 for the minimum rise rate value.
If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-
ply is met, one of the following configurations can be used:
A logic “0” value is applied during power-up on pin PA11 until VDDIN rises above 1.2V.
A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V.
6.2
Startup Considerations
This chapter summarizes the boot sequence of the AT32UC3L016/32/64. The behavior after
power-up is controlled by the Power Manager. For specific details, refer to the Power Manager
chapter.
6.2.1
Starting of Clocks
After power-up, the device will be held in a reset state by the Power-on Reset (POR18 and
POR33) circuitry for a short time to allow the power to stabilize throughout the device. After
reset, the device will use the System RC Oscillator (RCSYS) as clock source. Please refer to
Table 32-17 on page 783 for the frequency for this oscillator.
On system start-up, the DFLL is disabled. All clocks to all modules are running. No clocks have
a divided frequency; all parts of the system receive a clock with the same frequency as the Sys-
tem RC Oscillator.
When powering up the device, there may be a delay before the voltage has stabilized, depend-
ing on the rise time of the supply used. The CPU can start executing code as soon as the supply
is above the POR18 and POR33 thresholds, and before the supply is stable. Before switching to
a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above
the minimum level (1.62V).
6.2.2
Fetching of Initial Instructions
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset
address, which is 0x80000000. This address points to the first address in the internal flash.
The code read from the internal flash is free to configure the clock system and clock sources .
Please refer to the Power Manager and SCIF chapters for details.
相關(guān)PDF資料
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