參數(shù)資料
型號(hào)： AT40K40LV-3DQC
廠商： ATMEL CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 2304 CLBS, 40000 GATES, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 2/67頁(yè)
文件大?。?/td> 1589K
代理商： AT40K40LV-3DQC
10
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Figure 6. Some Single Cell Modes
LUT
2:1
MUX
LUT
DQ
Q
Q (Registered)
DQ
Synthesis Mode. This mode is particularly important for
the use of VHDL/Verilog design. VHDL/Verilog Synthesis
tools generally will produce as their output large amounts
of random logic functions. Having a 4-input LUT structure
gives efficient random logic optimization without the
delays associated with larger LUT structures. The output
of any cell may be registered, tri-stated and/or fed back
into a core cell.
Arithmetic Mode is frequently used in many designs.
As can be seen in the figure, the AT40K/AT40KLV core cell
can implement a 1-bit full adder (2-input adder with both
Carry In and Carry Out) in one core cell. Note that the
sum output in this diagram is registered. This output could
then be tri-stated and/or fed back into the cell.
DSP/Multiplier Mode. This mode is used to efficiently
implement array multipliers. An array multiplier is an array
of bitwise multipliers, each implemented as a full adder
with an upstream AND gate. Using this AND gate and the
diagonal interconnects between cells, the array multiplier
structure fits very well into the AT40K/AT40KLV
architecture.
Counter Mode. Counters are fundamental to almost all
digital designs. They are the basis of state machines,
timing chains and clock dividers. A counter is essentially
an increment by one function (i.e., an adder), with the
input being an output (or a decode of an output) from the
previous stage. A 1-bit counter can be implemented in one
core cell. Again, the output can be registered, tri-stated
and/or fed back.
Tri-state/Mux Mode. This mode is used in many
telecommunications applications, where data needs to be
routed through more than one possible path. The output of
the core cell is very often tri-statable for many inputs to
many outputs data switching.
A
B
C
D
A
B
C
A
B
C
D
A
B
C
EN
Q
SUM (Registered)
SUM
and/or
PRODUCT
or
CARRY
PRODUCT (Registered)
CARRY
CARRY IN
and/or
or
and/or
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT40K40LV-3DQI 功能描述:IC FPGA 3.3V 2304 CELL 208PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
AT40K40LV-3EQC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
AT40K40LV-3EQI 功能描述:IC FPGA 3.3V 2304 CELL 240PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
AT40K40LV-3FQC 制造商:Atmel Corporation 功能描述:FPGA 50K GATES 2304 CELLS COMM 0.6UM 3.3V 304PQFP - Trays
AT40K40LV-3FQI 功能描述:IC FPGA 3.3V 2304 CELL 304PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
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