參數(shù)資料
型號(hào)： AT40K40LV-3EQC
廠商： ATMEL CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 2304 CLBS, 40000 GATES, PQFP240
封裝： PLASTIC, QFP-240
文件頁(yè)數(shù)： 20/67頁(yè)
文件大小： 1589K
代理商： AT40K40LV-3EQC
27
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 4.75V, temperature = 70°C
Minimum times based on best case: VCC = 5.25V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL.
Clocks and Reset Input buffers are measured from a V
IH of 1.5V at the input pad to the internal VIH of 50% of VCC.
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
Cell Function
Parameter
Path
Device
-2
Units
Notes
Global Clocks and Set/Reset
GCLK Input Buffer
t
PD (Maximum)
pad -> clock
AT40K05
AT40K10
AT40K20
AT40K40
1.1
1.2
1.4
ns
Rising edge clock
FCLK Input Buffer
t
PD (Maximum)
pad -> clock
AT40K05
AT40K10
AT40K20
AT40K40
0.7
0.8
ns
Rising edge clock
Clock Column Driver
tPD (Maximum)
clock -> colclk
AT40K05
AT40K10
AT40K20
AT40K40
0.8
0.9
1.0
1.1
ns
Rising edge clock
Clock Sector Driver
t
PD (Maximum)
colclk -> secclk
AT40K05
AT40K10
AT40K20
AT40K40
0.5
ns
Rising edge clock
GSRN Input Buffer
tPD (Maximum)
pad -> GSRN
AT40K05
AT40K10
AT40K20
AT40K40
3.0
3.7
4.3
5.6
ns
From any pad to Global
Set/Reset network
Global Clock to Output
tPD (Maximum)
clock pad -> out
AT40K05
AT40K10
AT40K20
AT40K40
8.3
8.4
8.6
8.8
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
Fast Clock to Output
t
PD (Maximum)
clock pad -> out
AT40K05
AT40K10
AT40K20
AT40K40
7.9
8.0
8.1
8.3
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
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