參數(shù)資料
型號： AT76C453AC-MY19T
廠商： E2V TECHNOLOGIES PLC
元件分類： 圖像傳感器
英文描述： IMAGE SENSOR-CMOS, 708(H) X 494(V) PIXEL, 30fps, SURFACE MOUNT
文件頁數(shù)： 44/44頁
文件大?。?/td> 768K
代理商： AT76C453AC-MY19T
9
5446A–IMAGE–02/06
AT76C453AC-MY19T
5.4
Digital Control Interface
This block basically generates all timing signals required for the read out of the image array and
processing of the raw RGB output signal.
The block takes care of:
Video frame format definition: The number of clocks per line and the number of lines per
frame can be programmed (max. 1023 clocks/line and 1023 lines/frame). The video frame
should have at least 484 lines / frame and 800 clocks/line.
Vertical / horizontal mirroring
DPGA gain
Exposure time
Timing windows for analog signal processing
Interfacing with the embedded micro-controller
5.5
Timing Generator
This circuit generates the clock signals required by the different functions incorporated. To avoid
interference from the digital into the analog core the overall chip timing is properly tuned.
The timing generator supports the option to have different frame rates available at stable input
clock. Clock division factors of 2, 4, 8 and 16 can be selected. For the default 12 MHz input clock
the device supports frame-rates from 15 down to 1.875 fps. The maximum frame-rate is 30 fps
VGA for a minimum input clock frequency of 24 MHz.
6.
Device Control
6.1
Master/Slave Mode Operation
The device supports master/slave mode operation. In master mode the horizontal (HD) and ver-
tical (VD) synchronization signals are generated by the sensor. In slave mode these signals
have to supplied.
When pin INEXSY is left unconnected (or logic low level applied) the master mode is defined by
means of an internal pull down resistor. The HD and VD output signals are programmable with
the pixel clock resolution. This allows it to shape these signals with respect to the digital video
stream.
The slave mode is activated when pin INEXSY is connected to a logic high level. Now the HD
and VD pins are input. In this mode it is not possible to tune the position of the digital video with
respect to the applied HD and VD signals.
For external synchronization the device performs a rising edge detection on both the HD and VD
input signals. To avoid sensitivity for glitches some digital filtering is performed. The high and
low duration of the applied HD signal should be at least three clock periods to be detected as a
valid HD signal. For VD the minimum duration should be at least 2 clock periods. The maximum
supported frame-format is 1023 clks/line and 1023 lines/frame.
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