參數(shù)資料
型號(hào): AT89C5131A-PUTIM
廠商: Atmel
文件頁數(shù): 28/176頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K USB 32QFN
標(biāo)準(zhǔn)包裝: 260
系列: AT89C513x
核心處理器: C52X2
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: LED,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
配用: AT89STK-10-ND - KIT EVAL APPL MASS STORAGE
AT89STK-05-ND - KIT STARTER FOR AT89C5131
121
AT89C5131
4136C–USB–04/05
Bulk/Interrupt
Transactions
Bulk and Interrupt transactions are managed in the same way.
Bulk/Interrupt OUT
Transactions in Standard
Mode
Figure 59. Bulk/Interrupt OUT transactions in Standard Mode
An endpoint will be first enabled and configured before being able to receive Bulk or
Interrupt packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the cor-
responding endpoint, store the number of data bytes by reading the UBYCTLX and
UBYCTHX registers. If the received packet is a ZLP (Zero Length Packet), the
UBYCTLX and UBYCTHX register values are equal to 0 and no data has to be read.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUTB0
bit to allow the USB controller to accept the next OUT packet on this endpoint. Until the
RXOUTB0 bit has been cleared by the firmware, the USB controller will answer a NAK
handshake for each OUT requests.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct and the endpoint byte counter contains the number of bytes sent by the Host.
OUT
DATA0 (n bytes)
ACK
HOST
UFI
C51
Endpoint FIFO read byte 1
OUT
DATA1
NAK
RXOUTB0
Endpoint FIFO read byte 2
Endpoint FIFO read byte n
Clear RXOUTB0
OUT
DATA1
NAK
OUT
DATA1
ACK
RXOUTB0
Endpoint FIFO read byte 1
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