參數(shù)資料
型號(hào): AT89C5131A-RDTIL
廠商: Atmel
文件頁(yè)數(shù): 158/185頁(yè)
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K USB 64VQFP
標(biāo)準(zhǔn)包裝: 160
系列: AT89C513x
核心處理器: C52X2
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: LED,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: AT89STK-10-ND - KIT EVAL APPL MASS STORAGE
AT89STK-05-ND - KIT STARTER FOR AT89C5131
其它名稱: AT89C5131-RDTIL-ND
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 74
2008-2012 Microchip Technology Inc.
4.4.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
The upper boundary addresses for incrementing
buffers
The lower boundary addresses for decrementing
buffers
The address boundaries check for addresses less than
or greater than the upper (for incrementing buffers) and
lower (for decrementing buffers) boundary addresses
(not just equal to). Address changes can, therefore,
jump beyond boundaries and still be adjusted correctly.
4.5
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data re-ordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.5.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled in any of
these situations:
BWM bits (W register selection) in the MODCON
register are any value other than 15 (the stack
cannot be accessed using Bit-Reversed
Addressing)
The BREN bit is set in the XBREV register
The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or Post-
Increment Addressing and word-sized data writes. It
will not function for any other addressing mode or for
byte-sized data, and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB), and the offset associated with the Regis-
ter Indirect Addressing mode is ignored. In addition, as
word-sized data is a requirement, the LSb of the EA is
ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the Bit-Reversed Pointer.
Note:
The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the effective address.
When
an
address
offset
(such
as
[W7 + W2]) is used, Modulo Addressing
correction is performed but the contents of
the register remain unchanged.
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note:
Modulo
Addressing
and
Bit-Reversed
Addressing
should
not
be
enabled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority when active for the X WAGU and X
WAGU; Modulo Addressing will be dis-
abled. However, Modulo Addressing will
continue to function in the X RAGU.
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