型號: AT89C51AC3-RLTIM
廠商: Atmel
文件頁數(shù): 118/140頁
文件大小: 0K
描述: IC 8051 MCU FLASH 64K 44VQFP
標(biāo)準(zhǔn)包裝: 160
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
2009 Microchip Technology Inc.
DS70286C-page 77
dsPIC33FJXXXGPX06/X08/X10
6.0
RESET
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
POR: Power-on Reset
BOR: Brown-out Reset
MCLR: Master Clear Pin Reset
SWR: RESET Instruction
WDT: Watchdog Timer Reset
TRAPR: Trap Conflict Reset
IOPUWR: Illegal Opcode and Uninitialized W
Register Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1). A POR will clear all bits, except for
the POR bit (RCON<0>), that are set. The user can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXGPX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 8.
“Reset” (DS70192) in the “dsPIC33F
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com).
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
MCLR
VDD
Internal
Regulator
BOR
Sleep or Idle
RESET
Instruction
WDT
Module
Glitch Filter
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
VDD Rise
Detect
POR
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