參數(shù)資料
型號: AT89C51ED2-RDTUM
廠商: Atmel
文件頁數(shù): 67/137頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 64K 64VQFP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標準包裝: 800
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 50
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
35
4235K–8051–05/08
AT89C51RD2/ED2
13. Programmable Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The
PCA consists of a dedicated timer/counter which serves as the time base for an array of five
compare/capture modules. Its clock input can be programmed to count any one of the following
signals:
Peripheral clock frequency (FCLK PERIPH) ÷ 6
Peripheral clock frequency (FCLK PERIPH) ÷ 2
Timer 0 overflow
External input on ECI (P1.2)
Each compare/capture module can be programmed in any one of the following modes:
Rising and/or falling edge capture
Software timer
High-speed output
Pulse width modulator
Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog Timer",
When the compare/capture modules are programmed in the capture mode, software timer, or
high speed output mode, an interrupt can be generated when the module executes its function.
All five modules plus the PCA timer overflow share one interrupt vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins
are listed below. If one or several bits in the port are not used for the PCA, they can still be used
for standard I/O.
The PCA timer is a common time base for all five modules (see Figure 13-1). The timer count
source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 13-1) and can
be programmed to run at:
1/6 the
peripheral clock frequency (FCLK PERIPH)
1/2 the
peripheral clock frequency (FCLK PERIPH)
The Timer 0 overflow
The input on the ECI pin (P1.2)
The CMOD register includes three additional bits associated with the PCA (See Figure 13-1 and
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the watchdog function on module 4.
PCA Component
External I/O Pin
16-bit Counter
P1.2/ECI
16-bit Module 0
P1.3/CEX0
16-bit Module 1
P1.4/CEX1
16-bit Module 2
P1.5/CEX2
16-bit Module 3
P1.6/CEX3
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