參數(shù)資料
型號: AT89C51RB2-SLRIM
廠商: Atmel
文件頁數(shù): 114/127頁
文件大?。?/td> 0K
描述: IC MCU FLASH 8051 16K 5V 44-PLCC
標(biāo)準包裝: 1
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 剪切帶 (CT)
配用: AT89STK-11-ND - KIT STARTER FOR AT89C51RX2
其它名稱: AT89C51RB2SLRIMCT
87
AT89C51RB2/RC2
4180E–8051–10/06
Flash Registers and
Memory Map
The AT89C51RB2/RC2 Flash memory uses several registers for its management:
Hardware registers can only be accessed through the parallel programming modes
which are handled by the parallel programmer.
Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called "Extra Flash Memory", is not in the internal Flash program memory
addressing space.
Hardware Register
The only hardware register of the AT89C51RB2/RC2 is called Hardware Security Byte
(HSB).
Table 65. Hardware Security Byte (HSB)
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
When this bit is programmed (‘1’ value) the boot address is 0000h.
When this bit is unprogrammed (‘1’ value) the boot address is F800h. By default,
this bit is unprogrammed and the ISP is enabled.
Flash Memory Lock Bits
The three lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 66.
76
54
32
1
0
X2
BLJB
-
XRAM
LB2
LB1
LB0
Bit
Number
Bit
Mnemonic
Description
7X2
X2 Mode
Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset
(Default).
6BLJB
Boot Loader Jump Bit
Unprogrammed (‘1’ value) to start the user’s application on next reset at address
0000h.
Programmed (‘0’ value) to start the boot loader at address F800h on next reset
(Default).
5-
Reserved
4-
Reserved
3XRAM
XRAM Config Bit (only programmable by programmer tools)
Programmed to inhibit XRAM after reset.
Unprogrammed, this bit to valid XRAM after reset (Default).
2-0
LB2-0
User Memory Lock Bits (only programmable by programmer tools)
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