參數(shù)資料
型號(hào): AT89LP2052-20SU
廠商: Atmel
文件頁數(shù): 28/94頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 2K 20SOIC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 38
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲(chǔ)器容量: 2KB(2K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 616 (CN2011-ZH PDF)
34
3547J–MICRO–10/09
AT89LP2052/LP4052
Table 18-2 lists commonly used baud rates and how they can be obtained from Timer 1.
18.3
More About Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are trans-
mitted/received, with the LSB first. The baud rate is fixed at 1/2 the oscillator frequency. Figure
18-1 shows a simplified functional diagram of the serial port in Mode 0 and associated timing.
Transmission is initiated by any instruction that uses SBUF as a destination register. The “write
to SBUF” signal also loads a “1” into the ninth position of the transmit shift register and tells the
TX Control block to begin a transmission. The internal timing is such that one full machine cycle
will elapse between “write to SBUF” and activation of SEND.
SEND transfers the output of the shift register to the alternate output function line of P3.0, and
also transfers Shift Clock to the alternate output function line of P3.1. At the falling edge of Shift
Clock the contents of the transmit shift register are shifted one position to the right.
As data bits shift out to the right, “0”s come in from the left. When the MSB of the data byte is at
the output position of the shift register, the “1” that was initially loaded into the ninth position is
just to the left of the MSB, and all positions to the left of that contain “0”s. This condition flags the
TX Control block to do one last shift, then deactivate SEND and set TI.
Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Con-
trol unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next
clock phase.
RECEIVE enables Shift Clock to the alternate output function line of P3.1. At the falling edge of
Shift Clock the contents of the receive shift register are shifted one position to the left. The value
that comes in from the right is the value that was sampled at the P3.0 pin at rising edge of Shift
Clock.
As data bits come in from the right, “1”s shift out to the left. When the “0” that was initially loaded
into the right-most position arrives at the left-most position in the shift register, it flags the RX
Control block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.
Table 18-2.
Commonly Used Baud Rates Generated by Timer 1
Baud Rate
f
OSC (MHz)
SMOD1
Timer 1
C/T
Mode
Reload Value
Mode 0: 1 MHz
2
X
Mode 2: 375K
12
0
X
62.5K
12
102
F4H
19.2K
11.059
1
0
2
DCH
9.6K
11.059
0
2
DCH
4.8K
11.059
0
2
B8H
2.4K
11.059
0
2
70H
1.2K
11.059
0
1
FEE0H
137.5
11.986
0
1
F55CH
110
6
0
1
F958H
110
12
0
1
F304H
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