156
3706C–MICRO–2/11
AT89LP3240/6440
P4.2/RST cannot be connected directly to V
DD and any external capacitors connected to RST
must be removed.
All external reset sources must be removed.
If P4.3 needs to be debugged in systems using the crystal oscillator, the external clock option
should be selected. The quartz crystal and any capacitors on XTAL1 or XTAL2 must be
removed and an external clock signal must be driven on XTAL1. Some emulator systems may
provide a user-configurable clock for this purpose.
Figure 24-1. AT89LP3240/6440 On-Chip Debug Connections
24.2
Software Breakpoints
The AT89LP3240/6440 microcontroller includes a BREAK instruction for implementing program
memory breakpoints in software. A software breakpoint can be inserted manually by placing the
BREAK instruction in the program code. Some emulator systems may allow for automatic inser-
tion/deletion of software breakpoints. The Flash memory must be re-programmed each time a
software breakpoint is changed. Frequent insertions/deletions of software breakpoints will
reduce the endurance of the nonvolatile memory. Devices used for debugging purposes should
not be shipped to end customers. The BREAK instruction is treated as a two-cycle NOP when
OCD is disabled.
24.3
Limitations of On-Chip Debug
The AT89LP3240/6440 is a fully-featured microcontroller that multiplexes several functions on
its limited I/O pins. Some device functionality must be sacrificed to provide resources for On-
Chip Debugging. The On-Chip Debug System has the following limitations:
The Debug Clock pin (DCL) is physically located on that same pin as Port Pin P4.2 and the
External Reset (RST). Therefore, neither P4.2 nor an external reset source may be emulated
when OCD is enabled.
CLK = Internal RC
VDD
XTAL1
P4.2/RST
GND
DCL
DDA
CLK = External Clock
VDD
XTAL2
P4.2/RST
GND
DCL
DDA
XTAL1
CLK
CLK = Crystal Oscillator
VDD
P4.3
P4.2/RST
GND
DCL
DDA
XTAL1
XTAL2
AB
C