osc = frequency. Table 17" />
參數(shù)資料
型號(hào): AT89S4051-24PU
廠商: Atmel
文件頁(yè)數(shù): 9/46頁(yè)
文件大?。?/td> 0K
描述: MCU 8051 4K FLASH 24MHZ 20-PDIP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 18
系列: 89S
核心處理器: 8051
芯體尺寸: 8-位
速度: 24MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM
輸入/輸出數(shù): 15
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
17
3390E–MICRO–6/08
AT89S2051/S4051
Notes:
1. SMOD is located at PCON.7.
2. f
osc = frequency.
Table 17-1.
SCON – Serial Port Control Register
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
7
65
43
21
0
(SMOD = 0/1)(1)
Symbol
Function
FE
Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set
regardless of the state of SMOD.
SM0
Serial Port Mode Bit 0, (SMOD must = 0 to access bit SM0)
SM1
Serial Port Mode Bit 1
SM2
Enables the Automatic Address Recognition feature in modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received
9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In mode 1, if SM2 =
1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, SM2 should be 0.
REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8
The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired.
RB8
In modes 2 and 3, the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was
received. In mode 0, RB8 is not used.
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the
stop bit in the other modes, in any serial transmission. Must be cleared by software.
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop
bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
SM0
SM1
Mode
Description
Baud Rate(2)
0
shift register
f
osc/12
0
1
8-bit UART
variable
1
0
2
9-bit UART
f
osc/64 or fosc/32
1
3
9-bit UART
variable
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