參數(shù)資料
| 型號： | AT89S8253-24JC |
| 廠商： | Atmel |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU FLASH 12K 44PLCC |
| 標準包裝： | 27 |
| 系列： | 89S |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 24MHz |
| 連通性： | SPI，UART/USART |
| 外圍設備： | POR，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 12KB（12K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 內部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
24
3286P–MICRO–3/10
AT89S8253
Figure 14-2. SPI Block Diagram
Note:
1. The Write Data Buffer is only used in enhanced SPI mode.
The SPI has two modes of operation: normal (non-buffered write) and enhanced (buffered
write). In normal mode, writing to the SPI data register (SPDR) of the master CPU starts the SPI
clock generator and the data written shifts out of the MOSI pin and into the MOSI pin of the slave
CPU. Transmission may start after an initial delay while the clock generator waits for the next full
bit slot of the specified baud rate. After shifting one byte, the SPI clock generator stops, setting
the end of transmission flag (SPIF) and transferring the received byte to the read buffer (SPDR).
If both the SPI interrupt enable bit (SPIE) and the serial port interrupt enable bit (ES) are set, an
interrupt is requested. Note that SPDR refers to either the write data buffer or the read data buf-
fer, depending on whether the access is a write or read. In normal mode, because the write
buffer is transparent (and a write access to SPDR will be directed to the shift buffer), any attempt
to write to SPDR while a transmission is in progress will result in a write collision with WCOL set.
However, the transmission will still complete normally, but the new byte will be ignored and a
new write access to SPDR will be necessary.
Enhanced mode is similar to normal mode except that the write buffer holds the next byte to be
transmitted. Writing to SPDR loads the write buffer and sets WCOL to signify that the buffer is
full and any further writes will overwrite the buffer. WCOL is cleared by hardware when the buff-
ered byte is loaded into the shift register and transmission begins. If the master SPI is currently
idle, i.e. if this is the first byte, then after loading SPDR, transmission of the byte starts and
WCOL is cleared immediately. While this byte is transmitting, the next byte may be written to
SPDR. The Load Enable flag (LDEN) in SPSR can be used to determine when transmission has
started. LDEN is asserted during the first four bit slots of a SPI transfer. The master CPU should
first check that LDEN is set and that WCOL is cleared before loading the next byte. In enhanced
mode, if WCOL is set when a transfer completes, i.e. the next byte is available, then the SPI
immediately loads the buffered byte into the shift register, resets WCOL, and continues trans-
mission without stopping and restarting the clock generator. As long as the CPU can keep the
write buffer full in this manner, multiple bytes may be transferred with minimal latency between
bytes.
OSCILLATOR
8-BIT SHIFT REGISTER
READ DATA BUFFER
PIN
CONTR
OL
LOGIC
SPI CONTROL
SPI STATUS REGISTER
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
SELECT
SPI CLOCK (MASTER)
DIVIDER
÷4÷16÷64÷128
SPI CONTROL REGISTER
8
SPIF
WCOL
SPR1
MSTR
SPIE
CLOCK
LOGIC
CLOCK
MSB
S
M
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
MSTR
SPE
DORD
LSB
S
M
S
MISO
P1.6
MOSI
P1.5
SCK
1.7
SS
P1.4
SPR0
SPE
WRITE DATA BUFFER(1)
相關PDF資料 |
PDF描述 |
|---|---|
| 213931-2 | CONN RCPT 34POS W/CABLE HARDWARE |
| 213932-3 | M-SERIES KIT,V.35,34P,UNASSM |
| AT89S8253-24AI | IC 8051 MCU FLASH 12K 44TQFP |
| AT89S8253-24AC | IC 8051 MCU FLASH 12K 44TQFP |
| AT89LP4052-16XI | IC 8051 MCU FLASH 4K 20TSSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT89S825324JI | 制造商:Atmel Corporation 功能描述: |
| AT89S8253-24JI | 功能描述:8位微控制器 -MCU UNSAWN WAFER 20 MIL BACKGRIND - 24MHZ RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| AT89S8253-24JU | 功能描述:8位微控制器 -MCU 12kB Flash 256B RAM 2.7V-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| AT89S8253-24JU SL383 | 制造商:Atmel Corporation 功能描述:MCU 8-bit AT89 80C51 CISC 12KB Flash 3.3V/5V 44-Pin PLCC T/R |
| AT89S8253-24JU SL928 | 制造商:Atmel Corporation 功能描述:PLCC REVIS 'R' - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。